Three-Terminal Memory Circuit for Parallel Column Writing
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Solution Overview
Problem
Existing memory circuits face inefficiencies in writing data to multiple cells in a single column simultaneously, leading to increased write times and exacerbating write disturb events.
Innovation Solution
A memory circuit design that includes a memory array with three-terminal memory cells, allowing simultaneous writing to multiple cells in a column by controlling voltage combinations to avoid unpredictable states, thereby enhancing write efficiency and reducing write disturb events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data are written to multiple cells in a single column simultaneously using existing memory circuits, then write bandwidth is limited and write times are increased, but write disturb events are exacerbated
Solution Approach 1:
The memory array is segmented into multiple independent columns, each capable of simultaneous write operations. The write operation is divided into column-specific operations where each column can be programmed independently, allowing parallel writes across multiple columns while maintaining control over write disturb events within each column segment.
Solution Approach 2:
The patent implements dynamic control of word lines and bit lines to enable selective simultaneous programming of multiple cells within a column. The write operation dynamically activates only the necessary word lines and bit lines for the target cells, allowing flexible concurrent writes while managing voltage distribution to prevent write disturb events in non-target cells.
2Loss of time
If existing memory circuits write to multiple cells simultaneously, then overall write times are reduced, but write disturb events increase
Solution Approach 1:
The patent applies local quality control by enabling simultaneous write operations in specific columns while keeping other columns inactive or in a protected state. Each column can have different write operations occurring simultaneously, with localized voltage application only to the active column's selected cells, thereby reducing write disturb events in inactive columns while maintaining fast write times.
Solution Approach 2:
The patent uses column select lines and row decoders as intermediaries to control and isolate write operations. These intermediary components ensure that write voltages are precisely directed to target cells while preventing voltage propagation to non-target cells, enabling simultaneous writes without exacerbating write disturb events.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables increased write bandwidth and reduced overall write times without exacerbating write disturb events, improving the efficiency of data writing operations.
Implementation Method 1
the dielectric layer includes a ferroelectric material and the device is referred to as a ferroelectric random-access memory (FRAM or FeRAM) cell
Data Source
AI summary
A method of writing data to a memory array includes identifying a first data pattern corresponding to a first subset of memory cells arranged in a first line extending in a first array dimension and located at a first position along a second array dimension, identifying a second subset of memory cells corresponding to the first data pattern, the second subset of memory cells being arranged in a second line extending in the first array dimension and located at a second position along the second array dimension, and simultaneously programming the first and second subsets of memory cells to a first logic level.