Three-Terminal SOT-MRAM Structure for Low-Power Cache Writes

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Solution Overview

Problem

Current STT-MRAM technologies face challenges in achieving high write speed and low power consumption required for cache applications, with existing methods facing performance trade-offs in endurance and retention, and novel high frequency-assisted write operations being infeasible.

Innovation Solution

A 1T1S (one transistor, one selector) SOT-MRAM design utilizing a spin-orbit interaction effect to switch the magnetic moment of the free magnetic layer, reducing device footprint, magnetic resistance, and increasing cell density, with a three-terminal SOT-MRAM structure optimized for high-speed, low-power operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If STT-MRAM uses current-driven MTJ writing, then write operation is achieved, but power consumption is high and write speed is limited

Engineering Contradiction:

Improvewrite power consumptionVSAvoidwrite speed

Core Design Contradiction:

PowerVSProductivity

Solution Approach 1:

The patent replaces the conventional current-driven spin transfer torque mechanism with a voltage-driven magnetoelectric coupling mechanism. The voltage-controlled magnetic anisotropy layer generates magnetic field through voltage application, eliminating the need for high current flow through the MTJ. This substitution of the actuation mechanism directly reduces write power consumption while enabling faster write speeds through voltage control.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the fundamental operating parameter from current-driven to voltage-driven control. By applying voltage to the magnetoelectric coupling layer, the magnetic anisotropy is modulated, which in turn controls the magnetic state switching. This parameter change enables low-power operation since voltage application consumes significantly less power than the high currents required by conventional STT-MRAM.

Inventive Principle:

Principle #35Parameter changes

2Area of stationary object

If device footprint is reduced for higher density, then cell density increases, but write performance and speed are degraded

Engineering Contradiction:

Improvedevice footprintVSAvoidwrite performance

Core Design Contradiction:

Area of stationary objectVSProductivity

Solution Approach 1:

The patent segments the write operation into two independent components: the voltage-controlled magnetic anisotropy layer for magnetic state switching and the read current path through the MTJ. This segmentation allows the write operation to be performed without requiring high current through the confined MTJ structure, enabling small cell footprint while maintaining write performance. The write and read paths are functionally separated, allowing independent optimization.

Inventive Principle:

Principle #1Segmentation

3Reliability

If endurance and retention are improved, then reliability increases, but write speed and power consumption are compromised

Engineering Contradiction:

Improveendurance and retentionVSAvoidwrite power consumption

Core Design Contradiction:

ReliabilityVSPower

Solution Approach 1:

The patent introduces a magnetoelectric coupling layer as an intermediary between the voltage control electrode and the magnetic layers. This intermediary layer converts electrical voltage into magnetic field through magnetoelectric coupling, enabling indirect control of the magnetic state. This intermediary mechanism achieves reliable magnetic switching with minimal power consumption, as the voltage is applied to the dielectric layer rather than forcing high current through the magnetic tunnel junction.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The SOT-MRAM design achieves significant improvements in write current and speed, addressing the limitations of STT-MRAM by enhancing write performance and reducing power consumption, making it suitable for low-power cache applications.

Implementation Method 1

utilizing a spin-orbit interaction effect to switch the magnetic moment of the free magnetic layer

Methodology Applied

Scientific EffectSpin-orbit interaction:

Implementation Method 2

An STT-MRAM utilizes a magnetic tunneling junction (MTJ) written at least in part by a current driven through the MTJ

Methodology Applied

Scientific EffectSpin transfer torque:

Implementation Method 3

magnetic tunneling junction (MTJ)

Methodology Applied

Scientific EffectMagnetoresistance: Magnetoresistance

Data Source

PatentUS20250318438A1Magnetic device and magnetic random access memory

Publication Date: 2025.10.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A magnetic memory device includes a magnetic tunnel junction (MT)) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a selector layer coupled to the first terminal.