Three-Tier Memory Firmware Routing for Middle Sub-Block Precharge
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Solution Overview
Problem
Current methods for programming three-tier memory structures face challenges in precharging the middle sub block, leading to inefficiencies and reduced block size, which affects system capacity and management.
Innovation Solution
Implement a firmware scheme that routes data through reverse order programming to precharge the middle sub block via the source side, followed by sequential writing to the lower and upper sub blocks, and manages data relocation during garbage collection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If block size is increased to reduce block count and meet capacity requirements, then storage capacity is improved, but programming efficiency deteriorates and internal transfer speed decreases
Solution Approach 1:
The patent divides a large block into multiple sub-blocks (first sub-block, second sub-block, third sub-block) that can be programmed independently. This segmentation allows the system to maintain large block sizes for capacity while achieving efficient programming by processing smaller sub-blocks separately, resolving the contradiction between storage capacity and programming efficiency.
2Ease of operation
If traditional programming order is used for three-tier memory, then upper and lower sub blocks can be precharged, but the middle sub block cannot be precharged through source or drain gates
Solution Approach 1:
The patent inverts the traditional programming sequence by programming the middle sub-block first (before programming the upper and lower sub-blocks). This inversion allows the middle sub-block to be precharged through the source side via the lower sub-block, solving the precharge problem that existed in conventional programming orders while maintaining manageable complexity.
3Reliability
If middle sub block is programmed first through reverse order programming, then precharge through source side is achieved, but data routing complexity increases
Solution Approach 1:
The patent performs preliminary actions by first erasing and programming the middle sub-block before handling the upper and lower sub-blocks. This preliminary action establishes the middle sub-block in a known state and enables reliable precharging through the source side, while the firmware manages the increased routing complexity through systematic data movement and erasure sequences.
Data Source
AI summary
A three tier memory has an upper sub block, a lower sub block, and a middle sub block. In the present disclosure, rather than precharging the upper and lower sub blocks, use is made of the middle sub block using a firmware (FW) scheme. Upon receiving a write request from a host, the FW will route the data to the middle sub block (SB1) through reverse order programming (ROP) so that the SB1 is pre-charged through the source side through the lower sub block (SB0). Once the SB1 is written, data is then routed to the SB0 and then to the upper sub block (SB2). When there is a garbage collection (GC) request, the FW will move the data from the SB2 and then erase the SB2. Then the data moves from the SB0 and SB0 is erased. Finally, the data moves from the SB1 and then SB1 is erased.