Three-Transistor Memory Cell Array for Leakage-Resistant Reads
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Solution Overview
Problem
Existing PUF memories suffer from poor quality and reliability due to transistor leakage currents and mismatch issues, leading to reduced read boundaries and inconsistent probability in generating 0 or 1.
Innovation Solution
A memory array with a differential and single-ended operation mode, utilizing a three-transistor memory cell structure where a second transistor acts as an isolation transistor to minimize leakage currents, and provides 50% probability for successful read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a two-transistor memory cell structure is used, then device complexity is reduced, but leakage current increases causing worse read boundary and reduced reliability
Solution Approach 1:
The memory cell is segmented into three transistors with distinct functional roles: first and third transistors for data storage and second transistor for isolation. This segmentation allows the isolation transistor to specifically address leakage current issues without compromising the overall simplicity of the memory cell structure.
Solution Approach 2:
The second transistor acts as an intermediary isolation transistor positioned between the first and third transistors. This intermediary component specifically blocks leakage current paths while allowing controlled current flow during read operations, thereby improving read boundary without significantly increasing device complexity.
2Ease of manufacture
If existing PUF memory designs are used, then manufacturing process is simpler, but quality and reliability are poor due to element mismatch
Solution Approach 1:
The patent changes the operational parameters by introducing differential mode reading with controlled voltage applications to the first, second, and third transistors. This parameter change enables the memory cell to achieve 50% probability of generating 0 or 1 while maintaining manufacturing simplicity, thereby improving reliability without sacrificing ease of manufacture.
3Measurement precision
If differential mode operation is implemented, then read accuracy is improved, but device complexity increases
Solution Approach 1:
The memory cell structure is designed with multi-functionality to support both differential mode and single-ended mode operations using the same three-transistor architecture. This universality allows the device to achieve high read accuracy through differential mode when needed while maintaining simplicity through single-ended mode for other applications, without requiring separate complex circuits for each mode.
Data Source
AI summary
A memory array includes word line sets, each having a first, second, and third word lines; bit line sets, each having a first and second bit lines; and memory cells, each of the memory cells dispose at intersections of each of the word line sets and each of the bit line sets. Each of the memory cells has a first, second, and third control ends that are respectively coupled to the first, second, and third word lines of a corresponding word line set, and a first and second ends that are respectively coupled to the first and second bit lines of a corresponding bit line set. In a differential mode, reading is performed according to reading currents of the first and second ends. In a single-ended mode, reading is performed according to the read currents of the first or second ends and the reference current.