Three-Transistor Memory Structure Using Thyristor Hysteresis
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional DRAMs face challenges in reducing size while maintaining performance, due to issues like leakage current and increased complexity, particularly in 1T1C DRAM structures.
Innovation Solution
A memory structure utilizing a thyristor operating mechanism with a 3T architecture, featuring a substrate and three gate structures, allowing for high scalability and fast operation speed, with a gate-all-around design and thyristor-based operation to adjust hysteresis windows without complex doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If 1T1C DRAM structure is used, then memory size can be reduced, but leakage current increases and process complexity increases
Solution Approach 1:
The patent changes the operational parameters by using a thyristor-based 3T structure instead of 1T1C, utilizing the hysteresis window characteristics of thyristors to achieve stable data storage with reduced leakage current through parameter optimization of the transistor configuration
2Volume of moving object
If 1T1C DRAM structure is used, then memory size can be reduced, but process complexity increases
Solution Approach 1:
The patent optimizes the transistor configuration parameter by adopting a 3T thyristor structure with gate-all-around design, which simplifies the manufacturing process compared to 1T1C while achieving smaller effective memory cell footprint through improved spatial arrangement
3Ease of manufacture
If conventional DRAM structure is used, then manufacturing is simpler, but sensing margin is smaller
Solution Approach 1:
The patent enhances the sensing margin by utilizing the thyristor hysteresis window characteristic, which provides a larger current difference between logic 0 and logic 1 states, improving measurement precision while maintaining manufacturing feasibility through standard CMOS-compatible processes
4Ease of manufacture
If conventional DRAM structure is used, then manufacturing is simpler, but retention time is shorter
Solution Approach 1:
The patent improves retention time by utilizing the thyristor's bistable state characteristic with hysteresis window, which maintains stable data storage for longer durations without requiring frequent refresh operations, while remaining compatible with conventional manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3T DRAM structure achieves a large sensing margin, increased retention and read-disturb-free time, and improved endurance, with fast operation speed and scalability, outperforming traditional DRAMs in miniaturization and performance.
Implementation Method 1
The memory structure is operated by an operating mechanism of a thyristor... adjustment of hysteresis windows
Data Source
AI summary
A memory structure includes a substrate, a first gate structure, a second gate structure, a third gate structure, and channel bodies separated from each other and passing through the first gate structure, the second gate structure and the third gate structure along a first direction. The first gate structure, the second gate structure and the third gate structure are disposed on the substrate, and are separated from each other along the first direction and extend respectively along a second direction and a third direction. The first gate includes first, second and third island structures respectively extending along the third direction and separated from each other along the second direction. The third gate structure includes fourth, fifth and sixth island structures respectively extending along the third direction and separated from each other along the second direction.