Three-Transistor Pixel Circuit for Low-Voltage Electrophoretic Displays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing electrophoretic display devices face challenges with high withstand voltage requirements, leading to increased costs and power consumption, as well as reliability issues due to the need for high-voltage source drive signals and substrates.
Innovation Solution
The display device employs a configuration with three pixel transistors and a driver that manages signal potentials to reduce voltage requirements, using a first pixel transistor for writing, a second for holding capacitance, and a third for grounding, allowing for lower voltage operation while maintaining image holding capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If a high voltage source drive signal is applied to the source of the pixel transistor, then the display device can achieve proper image display, but the chip size increases due to increased withstand voltage requirements of the display IC
Solution Approach 1:
The pixel transistor is divided into multiple transistors (first pixel transistor, second pixel transistor, third pixel transistor) with separate functions. The first pixel transistor handles writing operations with lower voltage, the second handles holding capacitance, and the third connects to ground. This segmentation allows each transistor to operate at lower individual voltage levels while collectively achieving the required display performance, thereby reducing the withstand voltage requirements of the display IC and decreasing chip size.
2Illumination intensity
If a high voltage source drive signal is applied to the source of the pixel transistor, then the display device can achieve proper image display, but the cost increases due to higher withstand voltage requirements
Solution Approach 1:
The pixel transistor is divided into multiple transistors (first pixel transistor, second pixel transistor, third pixel transistor) with separate functions. The first pixel transistor handles writing operations with lower voltage, the second handles holding capacitance, and the third connects to ground. This segmentation allows each transistor to operate at lower individual voltage levels while collectively achieving the required display performance, thereby reducing the withstand voltage requirements of the display IC and decreasing chip size.
3Illumination intensity
If a high voltage source drive signal is applied to the source of the pixel transistor, then the display device can achieve proper image display, but power consumption increases
Solution Approach 1:
The pixel transistor is divided into multiple transistors (first pixel transistor, second pixel transistor, third pixel transistor) with separate functions. The first pixel transistor handles writing operations with lower voltage, the second handles holding capacitance, and the third connects to ground. This segmentation allows each transistor to operate at lower individual voltage levels while collectively achieving the required display performance, thereby reducing the withstand voltage requirements of the display IC and decreasing chip size.
4Illumination intensity
If a high voltage source drive signal is applied to the source of the pixel transistor, then the display device can achieve proper image display, but reliability decreases due to substrate withstand voltage requirements
Solution Approach 1:
The pixel transistor is divided into multiple transistors (first pixel transistor, second pixel transistor, third pixel transistor) with separate functions. The first pixel transistor handles writing operations with lower voltage, the second handles holding capacitance, and the third connects to ground. This segmentation allows each transistor to operate at lower individual voltage levels while collectively achieving the required display performance, thereby reducing the withstand voltage requirements of the display IC and decreasing chip size.
Data Source
AI summary
A display device includes: a first pixel transistor couples one electrode of holding capacitance to a first signal line; a second pixel transistor couples another electrode of the holding capacitance to a second signal line; a third pixel transistor couples the other electrode of the holding capacitance to a GND potential; and a driver that supplies a negative potential to the second signal line when the first signal line is supplied with a positive potential, supplies the GND potential to the second signal line when the first signal line is supplied with the GND potential, and supplies the positive potential to the second signal line when the first signal line is supplied with the negative potential. The first and second pixel transistors are on during a writing period and off during a holding period. The third pixel transistor is off during the writing period and on during the holding period.