Three-Value Multiplication via Digit Segmentation
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Solution Overview
Problem
Existing computer systems face challenges in accurately performing check procedures for reciprocal square root operations due to the complexity of multiplying three values, which is not trivial in typical hardware and often results in inaccurate results, especially in rounding modes like round towards zero, round away from zero, and round to nearest, leading to unreliable results and the omission of check procedures to avoid increased hardware costs.
Innovation Solution
A method and system that perform a comparison computation by separating the digits of an intermediate result into most significant and less significant portions, allowing for three multiply operations to accurately determine the result of multiplying three values, enabling a check procedure for reciprocal square root calculations without increasing the size of the multiplier logic, thus ensuring accurate results without significant area or power consumption increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a check procedure is implemented to verify the accuracy of reciprocal square root operations by multiplying three values, then measurement precision is improved, but device complexity increases because typical hardware multiplier logic is designed to multiply only two values
Solution Approach 1:
The patent segments the multiplication of three values into multiple two-value multiplication operations. The check parameter g = (r+c)²b is computed by first multiplying (r+c) × (r+c) to get an intermediate result, then multiplying that intermediate result by b. This segmentation allows the use of standard two-value multiplier logic while achieving the required three-value multiplication for accuracy verification.
Solution Approach 2:
The patent performs preliminary computation of the intermediate result (r+c)² before the final multiplication by b. This preliminary action allows the system to prepare the intermediate value and then use it in the subsequent multiplication, enabling the check procedure to be implemented using standard hardware multiplier logic designed for two-value operations.
2Measurement precision
If the size of multiplier logic is increased to directly multiply three values, then measurement precision is improved, but area increases
Solution Approach 1:
The patent segments the three-value multiplication into sequential two-value multiplications, avoiding the need for larger multiplier logic that would be required to directly compute the product of three values in a single operation. This segmentation maintains area efficiency while achieving the required precision.
3Measurement precision
If the size of multiplier logic is increased to directly multiply three values, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent segments the computation into multiple smaller multiplication steps rather than requiring a single large multiplier that would consume more power. By using standard-sized multipliers in sequence, the power consumption is reduced compared to implementing a larger multiplier logic unit that could directly handle three-value multiplication.
4Reliability
If check procedure is implemented to ensure accurate results, then reliability is improved, but latency increases due to additional computation steps
Solution Approach 1:
The patent performs the computation of (r+c)² as a preliminary step before the final multiplication by b. This preliminary computation of the intermediate result allows the check procedure to be structured in an efficient manner, computing values that are then reused in subsequent steps, thereby reducing the overall latency compared to computing everything from scratch.
Data Source
AI summary
A method and computer system are provided for performing a comparison computation, e.g. for use in a check procedure for a reciprocal square root operation. The comparison computation compares a multiplication of three values with a predetermined value. The computer system performs the multiplication using multiplier logic which is configured to perform multiply operations in which two values are multiplied together. A first and second of the three values are multiplied to determine a first intermediate result, w1. The digits of w1 are separated into two portions, w1,1 and w1,2. The third of the three values is multiplied with w1,2 and the result is added into a multiplication of the third of the three values with w1,1 to thereby determine the result of multiplying the three values together. In this way the comparison is performed with high accuracy, while keeping the area and power consumption of the multiplier logic low.