Three-Way Interconnect Topology for Low-Power PU Communication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits with multiple processing units face challenges in minimizing overall power consumption for point-to-two-point communication, as existing matrix structures with programmable wiring switches do not provide a minimal power consumption solution.
Innovation Solution
An integrated circuit design featuring at least three processing units connected through a multi-level metallization with a first three-way switch embedded in the metallization, forming an acute angle triangle with the interface points of the processing units, and optionally including isolation and second three-way switches to optimize power consumption without increasing capacitive load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a matrix structure with Manhattan or orthogonal signal routing is used, then the wiring layout is simplified, but the power consumption is not minimized
Solution Approach 1:
The patent applies asymmetry by using a triangular (non-orthogonal) routing topology instead of conventional Manhattan or orthogonal grid structures. The three-way switch connects to three processing units arranged in a triangular pattern, creating an asymmetric signal path that reduces the number of active switches needed for point-to-two-point communication, thereby minimizing power consumption while maintaining manufacturing feasibility.
Solution Approach 2:
The patent implements dynamic power management through the three-way switch that can selectively connect different processing units based on communication requirements. For point-to-two-point communication, only one switch path is active at a time, dynamically reducing the number of conducting switches and minimizing static and dynamic power consumption compared to always-active matrix structures.
2Speed
If conventional point-to-point interconnections are used, then the communication path is direct, but the overall power consumption is not minimized
Solution Approach 1:
The three-way switch serves multiple functions: it enables point-to-point communication between any pair of the three processing units and also supports point-to-two-point communication where one unit communicates with both others. This multi-functionality allows direct communication paths while minimizing the number of active switches, reducing power consumption compared to dedicated point-to-point connections for each pair.
3Use of energy by moving object
If isolation switches are placed in the substrate, then the static power consumption is reduced, but the capacitive load increases due to additional wiring
Solution Approach 1:
The patent merges the isolation switch function with the existing three-way switch structure embedded in the multi-level metallization. Rather than adding separate isolation switches in the substrate that would increase wiring capacitance, the design integrates switching and isolation capabilities into the same metallization layer, reducing additional capacitive load while maintaining static power consumption benefits through selective path activation.
Data Source
Figure 1a~1b
Figure 2~3
Figure 4
AI summary
An integrated circuit, comprising at least three PU (processing unit), a substrate comprising an active-part of each PU, a multi-level metallization, formed on the substrate, comprising a connection-part of the PU, and; an interconnection connecting the three PU; characterized in that the interconnection comprises a first three-way switch, connected to the three PU through three interconnect segments, wherein the capacitive loading of the three interconnect segments is less than the capacitive loading of any selected set of two minimum capacitive loading interconnect segments connecting the three PU.