Three-Wire Communication System With Embedded Clock Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed data communication in processors faces challenges with parallel communication techniques due to power supply noise and complexity, and serializer/deserializer (SerDes) technology is cumbersome and power-intensive, making it unsuitable for on-die communications.
Innovation Solution
A communication system using three wires with signaling logic levels of −1, 0, and +1 to embed clock signals within the data stream, minimizing the need for buffers and reducing electromagnetic interference, allowing for simultaneous data and clock signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If parallel data communication technique with buffers is used, then data communication rate can be achieved, but power supply noise increases due to large dynamic currents
Solution Approach 1:
The patent combines data and clock signals into a single integrated communication scheme using three wires. The clock signal is embedded within the data transmission itself through specific voltage level encoding, eliminating the need for separate clock buffering and reducing power supply noise while maintaining high data communication rates
2Speed
If SerDes technology is used, then data communication rate can be achieved, but device complexity and die area increase significantly
Solution Approach 1:
The patent extracts and eliminates the complex SerDes functionality by implementing a simplified three-wire communication scheme that directly encodes both data and clock information in voltage levels. This removes the need for serializer/deserializer circuits, significantly reducing device complexity and die area while maintaining high-speed communication capabilities
Solution Approach 2:
The patent replaces expensive, complex SerDes circuits with a simpler, more economical three-wire implementation using basic voltage level encoding. This disposable-like approach uses straightforward voltage comparisons rather than complex serialization/deserialization logic, reducing overall system cost and complexity
3Speed
If SerDes technology is used, then data communication rate can be achieved, but power consumption increases
Solution Approach 1:
By merging data and clock transmission into a single three-wire system with embedded timing information, the patent eliminates the separate power-intensive SerDes circuits. The combined approach uses simpler voltage level switching that consumes less power while achieving the same data communication rate
4Speed
If parallel data communication technique is used, then data communication rate can be achieved, but number of data lines and buffers increases
Solution Approach 1:
The patent transitions from traditional parallel communication dimensions to a three-dimensional voltage level encoding scheme. By using three voltage levels (-1, 0, +1) across three wires, the system achieves high data rates without requiring multiple parallel buffers, effectively adding a voltage level dimension to the communication protocol
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances signal strength, reduces power consumption, and minimizes electromagnetic interference, improving signal-to-noise ratio and reducing design complexity, making it suitable for high-speed on-die communications.
Implementation Method 1
A first comparator is coupled to a first output, wherein the first comparator is for generating data signals in response to the sign of voltages on the first data line minus voltages on the second data line
Implementation Method 2
A second comparator is coupled to a second output, wherein the second comparator is for generating clock signals in response to the sign of voltages on the third data line minus the average of voltages on the first and second data lines
Data Source
AI summary
A communication system includes a receiver for decoding data having three states of −1, 0, and 1. The receiver includes a first input coupled to a first data line, a second input coupled to a second data line, and a third input coupled to a third data line. A first comparator is coupled to a first output, wherein the first comparator is for generating data signals in response to the sign of voltages on the first data line minus voltages on the second data line. A second comparator is coupled to a second output, wherein the second comparator is for generating clock signals in response to the sign of voltages on the third data line minus the average of voltages on the first and second data lines.