Three-Wire Digital Interface Receiver for High-Speed Data
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Solution Overview
Problem
Current three-wire digital interfaces face challenges in supporting high data rates for LTE carrier aggregation due to high clock frequencies, leading to increased power consumption and complexity, particularly in phase locked loop synchronization, and require precise impedance matching which is difficult to achieve.
Innovation Solution
A receiver design for a three-wire digital interface that enables twelve different states of voltages or currents, allowing for high-speed data transmission with a low clock speed and long data symbols, reducing the need for precise impedance matching and minimizing power consumption by increasing input impedance, and incorporating a network with resistive elements in a star or triangular configuration to enhance noise immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high clock frequencies are used to support high data rates, then data transmission speed is improved, but power consumption increases
Solution Approach 1:
The patent employs Double Data Rate (DDR) encoding where data changes occur at both rising and falling edges of the clock signal, effectively doubling the data transmission rate for a given clock frequency. This allows achieving high data rates without proportionally increasing clock frequency and power consumption
Solution Approach 2:
The patent uses three-level voltage signals (high, intermediate, low) instead of traditional two-level signals, enabling six unique states for data coding. This allows log2(6)≈2.585 bits per symbol, increasing data transmission efficiency without requiring proportional increases in clock frequency
2Speed
If high clock frequencies are used for phase locked loop synchronization, then data transmission speed is improved, but power consumption becomes comparable to RFIC frequency synthesizer
Solution Approach 1:
The receiver extracts the clock signal directly from the incoming data symbols themselves, rather than using a separate high-frequency phase locked loop. The PLL operates at lower frequencies by locking to the symbol rate derived from the three-level signals, significantly reducing power consumption while maintaining synchronization
3Reliability
If precise impedance matching is required, then signal transmission quality is improved, but device complexity increases
Solution Approach 1:
The patent employs a balanced three-wire interface where the sum of voltages on the three wires is maintained at a constant reference level. This balanced configuration provides inherent common-mode noise rejection and reduces sensitivity to impedance variations, eliminating the need for precise impedance matching while maintaining signal integrity
4Productivity
If three-level signals are transmitted over three wires, then data transmission efficiency is improved, but voltage difference requirements between wires increase complexity
Solution Approach 1:
The three-wire interface serves multiple functions simultaneously: data transmission, clock extraction, and impedance balancing. The same three wires carry the three-level signals while their balanced configuration automatically provides clock recovery and noise immunity, eliminating the need for separate control lines or complex voltage management circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient high-speed data transmission with reduced power consumption and improved noise immunity, allowing for lower input currents and simplified design by relaxing the requirement for precise impedance matching and avoiding the need for a voltage reference.
Implementation Method 1
first resistive element coupled between the first input terminal and the first junction node; second resistive element coupled between the second input terminal and the second junction node; third resistive element coupled between the third input terminal and the third junction node
Data Source
AI summary
A receiver for a three-wire digital interface, a method for operating a three-wire digital interface, a signalling system comprising the receiver, and a wireless communication device comprising the signalling system. The receiver for a three-wire digital interface comprises a first resistive element coupled between a first input terminal and a first junction node, a second resistive element coupled between a second input terminal and a second junction node, and a third resistive element coupled between a third input terminal and a third junction node. A network comprising first second and third network terminals is coupled to first, second and third junction nodes. The network has substantially the same impedance between all pairs of the first, second and third network terminals.