Threshold-Based Data Encoding for Narrow Bus Bandwidth
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Solution Overview
Problem
Conventional digital signal processor devices face challenges in increasing data bandwidth from the core processor to memory, leading to wide buses and large memories that result in increased area, wire density, and power consumption, contradicting the goal of improving overall device performance.
Innovation Solution
The solution involves an apparatus with two circuits: one to store and generate data relative to varying thresholds, reducing data width by representing each data item as an index and a difference from a threshold, and another to reconstruct the data using these thresholds, allowing for data width reduction and efficient transfer over a narrow bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data bandwidth is increased from core processor to memory, then data transfer capability is improved, but bus width and memory size must be increased which increases area, wire density, and power consumption
Solution Approach 1:
The patent changes the parameter of data representation by introducing threshold-based encoding. Instead of using full-width data directly, the system encodes data as (index, difference) pairs where the index points to a threshold value and the difference represents the offset. This parameter transformation allows the same data to be represented with reduced bit width, thereby decreasing the bus width and memory area requirements while maintaining the ability to transfer data at high bandwidth.
Solution Approach 2:
The patent segments the data representation into two components: an index component that selects from a set of predefined thresholds and a difference component that represents the offset from the selected threshold. This segmentation allows the data to be encoded more efficiently, reducing the total number of bits needed and consequently reducing the bus width and memory area requirements.
2Productivity
If data bandwidth is increased from core processor to memory, then data transfer capability is improved, but bus width and memory size must be increased which increases power consumption
Solution Approach 1:
The patent changes the parameter of data representation by introducing threshold-based encoding. Instead of using full-width data directly, the system encodes data as (index, difference) pairs where the index points to a threshold value and the difference represents the offset. This parameter transformation allows the same data to be represented with reduced bit width, thereby decreasing the bus width and memory area requirements while maintaining the ability to transfer data at high bandwidth.
3Productivity
If data bandwidth is increased from core processor to memory, then data transfer capability is improved, but bus width and memory size must be increased which increases wire density
Solution Approach 1:
The patent changes the parameter of data representation by introducing threshold-based encoding. Instead of using full-width data directly, the system encodes data as (index, difference) pairs where the index points to a threshold value and the difference represents the offset. This parameter transformation allows the same data to be represented with reduced bit width, thereby decreasing the bus width and memory area requirements while maintaining the ability to transfer data at high bandwidth.
Data Source
AI summary
An apparatus having first and second circuits is disclosed. The first circuit may be disposed on a first side of a bus and configured to store thresholds in a first memory. Each threshold generally represents a respective one of a plurality of regular bit patterns in first data. The first circuit may also be configured to generate second data by representing each respective first data as (i) an index to one of the thresholds and (ii) a difference between the one threshold and the respective first data. A width of the bus may be narrower than the respective first data. The second circuit may be disposed on a second side of the bus and configured to (i) store the thresholds and a plurality of items in a second memory and (ii) reconstruct the first data by adding the respective thresholds to the second data in response to the items.