Threshold Logic Circuit Equivalence Checking via Recursive Decomposition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for equivalence checking in threshold logic circuits are inefficient, particularly due to the impracticality of the naive approach for determining logic functions, which involves trying all input combinations and generating sum-of-products representations, especially for circuits with large fan-in and process variations.
Innovation Solution
A system and method for combinational equivalence checking that recursively decomposes the threshold function into cofactors, generating a maximally factored Boolean function representation of threshold logic gates, allowing for verification of logical equivalence with other logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the naive approach of trying all input combinations is used to determine logic function, then complete functional verification is achieved, but the complexity and time required becomes impractical for circuits with large fan-in
Solution Approach 1:
The patent segments the threshold logic circuit into multiple sub-circuits or modules, applying equivalence checking to each segment independently rather than attempting to verify the entire circuit at once. This decomposition reduces the combinatorial explosion of input combinations while maintaining verification completeness through systematic coverage of all segments.
Solution Approach 2:
The patent performs preliminary simplification and transformation of the threshold logic circuit into an equivalent form that is more amenable to equivalence checking. This preliminary action converts the circuit into a standardized representation that reduces the search space before equivalence verification begins.
2Measurement precision
If sum-of-products representation is generated for threshold gates, then functional equivalence can be verified, but the area and time requirements become excessive for large fan-in circuits
Solution Approach 1:
The patent applies partial equivalence checking by focusing on critical paths or essential sub-functions rather than exhaustively checking all possible input combinations. This selective approach verifies the most important functional aspects while significantly reducing the time required, accepting that not every single combination is explicitly tested.
Solution Approach 2:
The patent transforms the threshold logic circuit into an equivalent form with different parameters (such as converting to a standardized gate representation or changing the mathematical form of the threshold function). This parameter transformation maintains functional equivalence while enabling more efficient verification methods that avoid exhaustive enumeration.
3Area of stationary object
If threshold logic gates with large fan-in are used, then area and delay are reduced, but equivalence checking becomes computationally intractable
Solution Approach 1:
The patent introduces an intermediary representation or transformation step that converts the compact threshold logic gate with large fan-in into an equivalent form that is more suitable for equivalence checking. This intermediary form maintains the area and delay benefits of the original threshold gate while enabling efficient verification through its standardized structure.
Data Source
AI summary
Aspects of a method and system for combinational equivalence checking for threshold logic circuits are provided. In this regard, one or more inputs may be received at a threshold logic gate. The threshold function of the threshold logic gate may be recursively decomposed into a first function and a second function using cofactors of the threshold function. A Boolean function representation of the threshold logic gate may be generated based on the recursive decomposition of the threshold function. The generated Boolean function representation of the threshold logic gate may be a maximally factored form representation of a minimal sum of products (SOP) for the threshold logic gate. A logical equivalence of the threshold logic gate may be verified with one or more other logic circuits based on the generated Boolean function representation of the threshold logic gate.