Threshold Logic FPGA Architecture for Lower PPA Overhead
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Solution Overview
Problem
Field-programmable gate arrays (FPGAs) lag behind application-specific integrated circuits (ASICs) in performance, power, and area (PPA) metrics, despite advancements in design mapping and architecture, and face challenges in efficiently implementing compute-intensive applications like convolutional neural networks (CNNs) and deep neural networks (DNNs.
Innovation Solution
A threshold logic FPGA (TLFPGA) architecture that integrates conventional lookup tables (LUTs) with complementary metal-oxide-semiconductor (CMOS) digital implementations of binary perceptrons, known as threshold logic cells (TLCs), which reduce configuration registers, multiplexer count, area, and power consumption while improving operating frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional LUTs are used to provide flexibility in programmability, then adaptability is improved, but area, power, and performance deteriorate
Solution Approach 1:
The patent uses lookup tables (LUTs) to store pre-computed threshold values that copy the functionality of complex threshold logic circuits. Instead of implementing threshold logic through multiple logic gates, the threshold values are pre-calculated and stored in LUTs, which then provide these values to simpler comparison circuits. This copying approach maintains the adaptability of threshold logic while significantly reducing the area and complexity of the hardware implementation.
2Adaptability or versatility
If conventional LUTs are used to provide flexibility in programmability, then adaptability is improved, but power consumption increases
Solution Approach 1:
The patent stores threshold values in lookup tables (LUTs) rather than implementing complex threshold logic circuits. The LUTs contain pre-computed threshold values that are copied to comparison circuits when needed. This approach reduces dynamic power consumption by eliminating the need for complex gate-level computations and reduces static power consumption by using simpler comparison logic instead of multiple logic gates, while maintaining full programmability through the LUT configuration.
3Adaptability or versatility
If conventional LUTs are used to provide flexibility in programmability, then adaptability is improved, but operating frequency decreases
Solution Approach 1:
The patent pre-computes and stores threshold values in lookup tables (LUTs), which are then copied to comparison circuits during operation. This eliminates the need for real-time complex logical operations, reducing the critical path delay and enabling higher operating frequencies. The LUTs provide immediate access to threshold values, allowing the comparison logic to operate faster while maintaining the same programmable functionality.
4Adaptability or versatility
If more LUT-Ks are added to the BLE block to increase functionality, then adaptability is improved, but area and power consumption increase
Solution Approach 1:
The patent implements a universal threshold logic cell that can perform multiple logic functions by programmably selecting different threshold values from the LUT. Instead of requiring separate dedicated circuits for each logic function, a single threshold logic cell with programmable thresholds can implement various logic operations (AND, OR, NAND, NOR, XOR, etc.) by loading appropriate threshold values. This multi-functionality approach significantly reduces the area required in the BLE block while maintaining comprehensive logic functionality.
Data Source
AI summary
A field-programmable gate array (FPGA) with reconfigurable threshold logic gates for improved performance, power, and area (PPA) is provided. This disclosure describes a new architecture for an FPGA, referred to as threshold logic FPGA (TLFPGA), that integrates a conventional lookup table (LUT) with a complementary metal-oxide-semiconductor (CMOS) digital implementation of a binary perceptron, referred to as a threshold logic cell (TLC). The TLFPGA design described herein, combined with a new logic mapping algorithm that exploits the presence of both conventional LUTs and TLCs within the basic logic element (BLE) block, achieves significant improvements in all the metrics of PPA. The TLCs of embodiments described herein are capable of implementing a complex threshold function, which if implemented using conventional gates would require several levels of logic gates. The TLCs only require seven static random-access memory (SRAM) cells and are significantly faster than the conventional LUTs.