Threshold Switching Memory Current Limitation via Decoder Activation

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Solution Overview

Problem

Threshold-type memories are susceptible to damage due to current spikes when memory cells threshold and conduct current, leading to undesirable conditions that can degrade or change the stored data.

Innovation Solution

The solution involves placing decoder circuits at both ends of access lines in a memory array, with the farther decoder circuits activated first to smooth current spikes by increasing the parasitic RC load, which acts as a filter to limit the magnitude of the current spike, thereby reducing the risk of disturbing the stored state.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a voltage is provided across a memory cell to access stored data, then the memory cell can be read, but a current spike occurs when the memory cell thresholds and begins to conduct current, which may damage the cell or degrade the stored data

Engineering Contradiction:
Improvememory cell integrityVSAvoidcurrent spike damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The decoder circuit is activated in advance before the memory cell is selected, preparing the circuit path and reducing the sudden current surge when the cell thresholds. This preliminary activation smooths the transition and prevents harmful current spikes.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The decoder circuit acts as an intermediary between the voltage source and the memory cell, controlling and limiting the current flow. By inserting this intermediate component, the harmful direct connection that causes current spikes is eliminated.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If decoder circuits are placed at both ends of access lines with farther circuits activated first to smooth current spikes, then current spike magnitude is reduced, but device complexity increases due to additional decoder circuits and control logic

Engineering Contradiction:
Improvecurrent spike magnitudeVSAvoiddecoder circuit configuration
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The decoder functionality is segmented into multiple distributed decoder circuits placed at different locations along the access lines. This segmentation allows localized current control at each segment, reducing overall current spike magnitude while distributing the complexity across multiple simple units rather than one complex centralized decoder.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces or eliminates current spikes during memory cell selection, minimizing the risk of damage to the memory cells and maintaining data integrity.

Implementation Method 1

the farther decoder circuits activated first to smooth current spikes by increasing the parasitic RC load, which acts as a filter to limit the magnitude of the current spike

Methodology Applied
Scientific EffectParasitic RC load filtering: Filter (electronic)

Data Source

PatentUS10410718B2Apparatuses and methods for current limitation in threshold switching memories
Publication Date: 2019.09.10 MICRON TECHNOLOGY INC
  • US10410718B2 patent drawing
  • US10410718B2 patent drawing
  • US10410718B2 patent drawing

AI summary

Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell.