Threshold Transition Analysis for Real-Time PAM-N Clock Recovery

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Solution Overview

Problem

Current clock data recovery methods for high data rate serial signals, such as PAM-N signals, face challenges in real-time recovery due to latency issues and are not effective in handling large data rates without prior decoding of the input signal.

Innovation Solution

A signal analysis method that determines threshold transition times and time intervals between them based on predefined conditions, allowing for the identification of symbol transitions without prior decoding, and uses these conditions to decode the input signal and recover the clock signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If phase interpolation techniques are used for clock data recovery, then frequency shifts can be tracked, but latency increases due to feedback requirements

Engineering Contradiction:
Improvefrequency shift tracking capabilityVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by detecting edges in advance and using them to determine sampling times for clock signal generation. This proactive approach eliminates the need for feedback loops, thereby reducing latency while maintaining the ability to track frequency shifts through the relationship between edge positions and clock phases.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If blind oversampling with high sampling rate is used, then sampling accuracy improves, but real-time recovery capability is lost for high data rates

Engineering Contradiction:
Improvesampling accuracyVSAvoidreal-time recovery capability
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent extracts only the essential information needed for clock recovery by detecting edges in the data signal. Instead of processing all sampled data points, it selectively uses edge positions to determine sampling times, thereby maintaining sampling accuracy while enabling real-time recovery for high data rates by reducing processing overhead.

Inventive Principle:
Principle #2Taking out (Extraction)

3Loss of time

If analog components are used in PLL based clock recovery, then delays in feedback are minimized, but device complexity increases

Engineering Contradiction:
Improvefeedback delayVSAvoidanalog component requirements
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent replaces the mechanical/analog PLL feedback system with a digital approach that uses edge detection and position-based sampling time determination. This substitution eliminates the need for analog components while maintaining low latency through direct calculation of sampling times from edge positions, thereby reducing device complexity without sacrificing feedback speed.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11121850B1Signal analysis method and signal analysis module
Publication Date: 2021.09.14 ROHDE & SCHWARZ GMBH & CO KG
  • US11121850B1 patent drawing
  • US11121850B1 patent drawing

AI summary

A signal analysis method is described. The signal analysis method comprises: receiving an N-ary input signal, the input signal comprising a symbol sequence; determining at least two threshold transition times of the input signal within a predetermined time period, wherein the input signal respectively crosses an amplitude threshold of several predetermined amplitude thresholds at each of the threshold transition times; determining time intervals between the threshold transition times; evaluating the time intervals based on a set of predefined conditions; and assigning the threshold transition times to at least one symbol transition based on the evaluation. Further, a signal analysis module is described.