Threshold Translation Engine for NAND Read Voltage Optimization
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Solution Overview
Problem
Flash storage devices face challenges in efficiently adapting to varying NAND register formats, leading to CPU-intensive operations and inefficiencies in encoding optimized read voltage threshold offsets, which results in delayed read operations and increased costs due to the need for frequent firmware updates and revalidation.
Innovation Solution
A threshold translation engine is implemented in the controller to translate and encode read voltage threshold offsets into a joint read voltage threshold offset, using a configuration table with shift values for each page type, allowing for efficient storage and reduction in instruction complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If read voltage threshold offsets are computed and stored separately for each page type (LP, UP, MP) in serialized pipeline format, then the thresholds can be optimized for specific gray code layouts, but the CPU-intensive operations and instruction complexity increase significantly
Solution Approach 1:
The patent combines multiple separate read voltage threshold offsets (for LP, UP, MP pages) into a single joint read voltage threshold offset value. This consolidation reduces the number of separate values that must be computed, stored, and processed, thereby reducing CPU-intensive operations and instruction complexity while maintaining the ability to optimize read thresholds for different page types through the unified joint offset value.
2Adaptability or versatility
If firmware is updated frequently to adapt to varying NAND register formats, then adaptability to different formats is improved, but costs increase due to revalidation requirements
Solution Approach 1:
The patent implements a configurable parameter system where the joint read voltage threshold offset can be adjusted based on different NAND register formats and page types. This allows the system to adapt to varying formats through parameter configuration rather than requiring firmware updates, thereby maintaining adaptability while avoiding the costs associated with frequent firmware revalidation and updates.
3Measurement precision
If separate optimized thresholds are computed for each page type, then read accuracy for specific page types is improved, but processing time increases due to serialized pipeline operations
Solution Approach 1:
The patent performs preliminary computation of a joint read voltage threshold offset that can be applied across different page types, reducing the need for separate real-time computations during read operations. This preliminary action maintains read accuracy by providing optimized threshold values while reducing processing time by avoiding repeated serialized pipeline operations for each page type.
Data Source
AI summary
Aspects of a storage device are provided that simplify the encoding or translation of optimized read voltage thresholds into a given NAND register format, which may vary depending on NAND technology, block type, page type, or gray code layout. The storage device may include a memory, a circuit that is configured to shift and combine read threshold voltage offsets into a joint read voltage threshold offset, and a controller configured to store the joint read voltage threshold offset in the memory. The circuit may be implemented in hardware of the controller. Alternatively, the controller software or firmware itself may shift and combine the read threshold voltage offsets into the joint read voltage threshold offset. As a result, the number of instructions that the controller typically performs in translating the optimized thresholds may be reduced. Moreover, the simplified translation may be scalable to different NAND technologies or page types.