Adjusting Transistor Threshold Voltages via Gate Stack Composition
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Solution Overview
Problem
Current semiconductor devices face challenges in efficiently managing threshold voltages across different transistors, particularly in achieving precise control and adjustment to optimize performance in various regions of the device.
Innovation Solution
The semiconductor device incorporates a substrate with strategically positioned dielectric films and gate stacks, including TiAlC, LaO, and TiN films, to create transistors with adjusted threshold voltages. These films are carefully stacked and configured to ensure distinct threshold voltages for different transistors, allowing for optimized performance across different regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple transistors with different threshold voltages are created using conventional methods, then transistor performance can be optimized for different regions, but the manufacturing process becomes complex and difficult to control
Solution Approach 1:
The patent applies local quality by forming gate stacks with different compositions at different locations on the substrate. Specifically, first gate stacks contain a first metal film with a first composition while second gate stacks contain a second metal film with a second composition, enabling each region to have optimized threshold voltage characteristics tailored to its specific functional requirements.
Solution Approach 2:
The patent changes the compositional parameter of the metal films in the gate stacks to achieve different threshold voltages. By varying the metal composition (first composition vs. second composition) in different gate stacks, the invention enables precise control over transistor threshold voltages without complicating the overall manufacturing process.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a substrate including a first region and a second region. First and second dielectric films are positioned above the substrate in the first region and the second region, respectively. First and second gate stacks are disposed on the first and second dielectric films, respectively. The first gate stack includes a first TiAlC film in direct contact with the first dielectric film, and a first barrier film and a first metal film sequentially stacked on the first TiAlC film. The second gate stack includes a first LaO film in direct contact with the second dielectric film. A second TiAlC film, a second barrier film, and a second metal film are sequentially stacked on the first LaO film.