Threshold Voltage Margin Read for Imminent Memory Failure Detection
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Solution Overview
Problem
Current memory systems, especially in low-cost computer systems and safety-critical applications like automotive systems, face challenges in predicting and detecting imminent read failures in non-volatile memory (NVM) before they become uncorrectable, which can lead to catastrophic errors.
Innovation Solution
The implementation of a threshold voltage technique that combines error correcting code (ECC) with a margin read at a different voltage level to detect imminent read failures, using a circuit with an address sequencer, ECC circuit, and threshold voltage level adjuster to identify uncorrectable errors, and a time-based approach to monitor increasing error corrections over time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC is used to correct read errors in NVM, then reliability is improved, but the ability to detect imminent failures before they occur is insufficient
Solution Approach 1:
The patent performs margin reads at shifted threshold voltages before actual failures occur. By proactively testing memory cells at stressed voltage conditions (Vt + ΔV and Vt - ΔV), the system detects cells that are approaching failure thresholds, enabling preventive action before uncorrectable errors occur in normal operation.
Solution Approach 2:
The patent changes the read verify voltage parameter from the normal Vt to margin voltages (Vt + ΔV and Vt - ΔV). This parameter shift allows detection of cells whose threshold voltages are drifting toward failure points, providing early warning of imminent read failures that would not be detectable at normal operating voltages.
2Measurement precision
If margin reads are performed at shifted threshold voltages to detect imminent failures, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent makes the existing ECC circuit perform multiple functions: it not only corrects errors during normal reads but also detects imminent failures during margin reads at shifted voltages. The same ECC logic and error correction mechanisms are reused for both error correction and failure prediction, avoiding the need for separate dedicated detection hardware.
Solution Approach 2:
The memory system performs self-diagnosis by using its own read circuitry and ECC mechanisms to detect imminent failures. The system monitors its own health status through margin reads and uses its existing error correction capabilities to identify cells approaching failure, eliminating the need for external or separate monitoring systems.
3Measurement precision
If multiple AI checks at different voltage levels are performed, then imminent failure detection is improved, but loss of time increases
Solution Approach 1:
The patent implements periodic array integrity checks at different voltage levels (normal Vt, Vt + ΔV, and Vt - ΔV) to monitor memory cell health over time. By performing these checks at scheduled intervals rather than continuously, the system balances detection accuracy with time consumption, identifying trends in threshold voltage drift while maintaining acceptable diagnostic overhead.
4Reliability
If ECC correctable reads are identified and followed by margin reads, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent applies margin reads selectively only to memory cells that exhibited correctable errors during normal reads, rather than performing margin reads on all cells. This partial action approach focuses diagnostic resources on cells that actually show signs of degradation, maintaining high reliability for problematic cells while minimizing the impact on overall system productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method provides accurate prediction of imminent read failures, reducing the number of non-defective parts returned to vendors and ensuring safety in critical applications by identifying uncorrectable errors before they occur, thereby enhancing memory system reliability.
Implementation Method 1
determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity (AI) check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent AI check at a margin read verify voltage level
Data Source
AI summary
A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.