Threshold Voltage Modulation in CMOS Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in scaling down transistors is the increase in gate leakage due to reduced gate dielectric layer thickness, which is exacerbated by the Fermi level pinning effect when using high-k materials, making it difficult to achieve appropriate threshold voltages for CMOS devices.
Innovation Solution
A method involving the formation of gate stacks with a high-k dielectric layer, a threshold voltage modulation layer, and specific work function layers, including titanium nitride and oxidation suppressing layers, to independently modulate the threshold voltages of N-channel and P-channel transistors, utilizing a germanium-containing channel region and dual-layer titanium nitride for P-channel transistors and a lanthanum-based modulation layer for N-channel transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate dielectric layer thickness is reduced to improve transistor performance, then the transistor performance is improved, but gate leakage increases
Solution Approach 1:
The patent uses a composite gate dielectric structure consisting of a high-k dielectric layer (such as HfO2, HfSiO, or HfSiON) combined with an oxidation suppressing layer (such as silicon nitride or silicon oxynitride). This composite structure provides both the high dielectric constant needed for thin equivalent oxide thickness and the oxidation resistance to prevent metal gate degradation, thereby reducing gate leakage while maintaining transistor performance.
2Loss of energy
If high-k material is used to reduce gate leakage, then gate leakage is reduced, but Fermi level pinning effect increases threshold voltage
Solution Approach 1:
The patent introduces an oxidation suppressing layer as an intermediary between the high-k dielectric layer and the metal gate electrode. This intermediary layer prevents direct contact between the metal gate and high-k material, thereby eliminating the Fermi level pinning effect while maintaining the benefits of high-k materials for reducing gate leakage.
Solution Approach 2:
The patent changes the work function parameter of the gate stack by using a metal gate electrode with可控 work function (such as tungsten, titanium, or tantalum) instead of polysilicon. By combining this with the oxidation suppressing layer, the threshold voltage can be precisely controlled without the Fermi level pinning effect that occurs with polysilicon gates.
3Reliability
If metal gate electrodes are formed to overcome Fermi level pinning, then Fermi level pinning is overcome, but it becomes difficult to form both N-type and P-type work function gates
Solution Approach 1:
The patent applies local quality by forming different work function layers in different regions of the semiconductor device. N-type metal gate electrodes (with lower work function) are formed in NMOS regions, while P-type metal gate electrodes (with higher work function) are formed in PMOS regions. This is achieved through selective deposition and etching processes that create region-specific gate characteristics.
Solution Approach 2:
The patent segments the gate formation process into distinct steps for different transistor types. The metal gate electrode formation is divided into separate N-type gate formation and P-type gate formation sequences, allowing independent optimization of work functions for NMOS and PMOS devices while using the same high-k dielectric and oxidation suppressing layer structure.
4Reliability
If effective work function is controlled to modulate threshold voltage, then threshold voltage modulation is achieved, but process variations (etching, thermal processing) change the effective work function
Solution Approach 1:
The patent provides beforehand cushioning by forming a robust oxidation suppressing layer that protects the metal gate electrode from oxidation during subsequent thermal processing and etching steps. This protective layer acts as a buffer that prevents process variations from altering the metal gate's work function, thereby stabilizing the threshold voltage against manufacturing variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for independent modulation of threshold voltages in CMOS devices, preventing increases in effective work function and enhancing performance by controlling the work function of gate stacks, thereby addressing the Fermi level pinning issue and improving transistor performance.
Implementation Method 1
forming a high-k dielectric layer over the substrate
Implementation Method 2
forming an oxidation suppressing layer over the first work function layer of the NMOS region
Data Source
AI summary
A method of fabricating a semiconductor device. A substrate (PMOS/NMOS regions) is prepared. A high-k dielectric layer is formed over the substrate. A threshold voltage modulation layer is formed over the dielectric layer of the NMOS region. A first work function layer is formed over the threshold voltage modulation layer and the dielectric layer of the PMOS region. An oxidation suppressing layer is formed over the first work function layer of the NMOS region. A second work function layer is formed over the oxidation suppressing layer and the first work function layer of the PMOS region. A first gate stack including the dielectric layer, the first work function layer and the second work function layer is formed over the PMOS region. A second gate stack including the dielectric layer, the threshold voltage modulation layer, the first work function layer and the oxidation suppressing layer is formed over NMOS region.