Through Array Contact for 3D Memory Vertical Interconnects
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Solution Overview
Problem
The challenge in semiconductor technology is the increasing complexity and cost of fabricating planar memory cells as they shrink in size, which can be addressed by transitioning to three-dimensional (3D) memory architectures, but these require efficient interconnect structures to manage vertical interconnects and reduce metal levels.
Innovation Solution
The development of a 3D NAND memory device with a staircase structure and through array contact (TAC) structures that use a single-material dielectric structure for vertical interconnects, allowing for reduced metal levels and simplified etching processes, thereby decreasing fabrication complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are continuously scaled down, then memory density increases, but fabrication complexity and cost increase
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) stacked memory architecture. Multiple memory layers are stacked vertically, with through-array contacts (TACs) providing vertical interconnects through the stack. This dimensional change allows continued density improvement without proportionally increasing fabrication complexity, as the vertical stacking approach simplifies certain interconnect requirements compared to continued planar scaling.
2Manufacturing precision
If complex etching processes are used for vertical interconnects, then interconnect precision improves, but fabrication complexity increases
Solution Approach 1:
The patent segments the etching process into distinct stages with different objectives. First, through-array contact holes are etched through the entire memory stack using a single-material dielectric layer, which simplifies the etch chemistry and process control. Second, smaller contact holes are etched within the TAC regions to reach specific conductor layers. This segmentation allows each etching stage to be optimized independently, maintaining precision while reducing overall process complexity compared to attempting to etch all features in a single complex process.
Solution Approach 2:
The patent employs local quality by using a single-material dielectric layer specifically in the TAC regions, rather than using alternating dielectric materials throughout the entire structure. This localized material simplification eases the etching process in critical vertical interconnect regions, as a single material requires only one etch chemistry and process condition set, thereby maintaining precision while reducing etching process complexity in the most critical areas.
Data Source
AI summary
Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.