3D NAND Through-Array Contacts for Dielectric-Only Vertical Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to increasing complexity and cost as feature sizes approach limits, necessitating a transition to three-dimensional (3D) memory architectures to enhance memory density.
Innovation Solution
The development of three-dimensional NAND memory devices with through array contact (TAC) structures, utilizing a stack of alternating dielectric layers to facilitate vertical interconnects and reduce manufacturing complexity and cost, includes a barrier structure and slit structures to separate regions and form conductive connections between memory fingers and peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology and circuit design, then memory density is improved, but manufacturing complexity and cost increase as feature sizes approach lower limits
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture. The 3D memory array is stacked vertically over the peripheral devices, utilizing the vertical dimension to achieve higher memory density without further reducing lateral feature sizes. This dimensional change resolves the contradiction by providing continued density scaling while avoiding the manufacturing complexity associated with sub-limits planar scaling.
2Ease of operation
If alternating conductor/dielectric stacks are used to provide vertical interconnects, then interconnect functionality is achieved, but etching difficulty and manufacturing complexity increase
Solution Approach 1:
The patent extracts the through-array contact formation from the complex alternating conductor/dielectric stack environment. By creating openings through the alternating dielectric stack in a separate, simplified process step, the formation of vertical interconnects is decoupled from the complex stack fabrication. This allows the interconnect functionality to be achieved while avoiding the etching difficulties associated with the alternating conductor/dielectric layers.
Solution Approach 2:
The patent segments the fabrication process into distinct stages: first forming the alternating dielectric stack with memory holes, then separately forming the through-array contact openings. This segmentation allows each process to be optimized independently, with the TAC openings being formed through a simpler dielectric-only stack rather than attempting to etch through alternating conductor/dielectric layers.
3Reliability
If barrier structures and slit structures are added to separate regions and form conductive connections, then region separation and electrical connectivity are improved, but device structure complexity increases
Solution Approach 1:
The barrier structure serves multiple functions simultaneously: it laterally separates the first region (alternating dielectric stack) from the second region (alternating conductor/dielectric stack), provides vertical extent to define region boundaries, and works in conjunction with slit structures to enable proper electrical connectivity. This multi-functionality achieves reliable region separation without proportionally increasing structural complexity.
Solution Approach 2:
The slit structures act as intermediaries between the barrier structures and the memory fingers. These slits extend through the alternating conductor/dielectric stack and provide the conductive pathways necessary for electrical connectivity while the barrier structures provide the lateral separation. The intermediary slit structures enable both regions to maintain their distinct functions while achieving proper electrical interconnection.
Data Source
Figure 1
Figure 2
Figure 3A
AI summary
Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes a substrate including a peripheral circuit, and an alternating layer stack disposed on the substrate. The alternating layer stack includes a first region including an alternating dielectric stack, a second region including an alternating conductor/dielectric stack, and a third region including staircase structures on edges of the alternating conductor/dielectric layer stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region or the third region, multiple channel structures and multiple slit structures each extending vertically through the alternating conductor/dielectric stack, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with the peripheral circuit.