Through-Body-Via Capacitors for High-Density On-Chip Capacitance

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Solution Overview

Problem

Existing technologies face challenges in providing sufficient on-chip capacitance for compact electronic devices, as traditional capacitors are either too large or offer limited capacitance, and through-silicon vias (TSVs) typically minimize capacitance to avoid signal delay.

Innovation Solution

The integration of through-body-vias (TBVs) within a semiconductor layer, accompanied by a dielectric layer between the TBV and the semiconductor, forms a TBV capacitor. This configuration can utilize a low-resistivity semiconductor layer as one electrode or a conductive layer between the semiconductor and dielectric as the other electrode, creating a metal-insulator-metal (MIM)-type capacitive structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional capacitors are used to provide on-chip capacitance, then sufficient capacitance can be achieved, but the device area occupied is too large

Engineering Contradiction:
ImprovecapacitanceVSAvoiddevice area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent transitions from planar capacitor structures to three-dimensional vertical structures by forming capacitors that extend through the substrate thickness. The first and second capacitors are positioned at different depths (first capacitor in first substrate region, second capacitor in second substrate region), utilizing the vertical dimension to increase capacitance density without occupying additional lateral device area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent embeds capacitor structures within the substrate volume by forming through-substrate vias and positioning capacitors at different vertical levels. The first conductive layer, dielectric layer, and second conductive layer are nested within the substrate, with the first capacitor structure containing the first conductive layer and dielectric layer, while the second capacitor structure contains the second conductive layer and dielectric layer, creating a nested three-dimensional arrangement that maximizes capacitance within limited space.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Speed

If through-silicon vias (TSVs) are used for electrical connection, then vertical connectivity is achieved, but capacitance is minimized to avoid signal delay

Engineering Contradiction:
Improvesignal speedVSAvoidcapacitance
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent makes the through-substrate via structures serve dual functions: they provide vertical electrical connectivity (original TSV function) and simultaneously form capacitor structures (new function). The first through-substrate via forms the first capacitor with the first conductive layer and dielectric layer, while the second through-substrate via forms the second capacitor with the second conductive layer and dielectric layer. This multi-functionality allows the same vertical connection structures to provide both signal connectivity and desired capacitance without compromising signal speed.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach provides significantly increased on-chip capacitance, potentially doubling or quintupling that of traditional MIM capacitors, while reducing signal delay and costs associated with off-chip solutions.

Implementation Method 1

a dielectric layer between the first conductive layer and the second conductive layer, wherein the first capacitor is formed by the first conductive layer, the dielectric layer and the second conductive layer

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentEP3311401B1On-chip through-body-via capacitors and techniques for forming same
Publication Date: 2025.02.26 INTEL CORP
  • EP3311401B1 patent drawingFigure 1A~1B
  • EP3311401B1 patent drawingFigure 1C~1D
  • EP3311401B1 patent drawingFigure 2A~2B

AI summary

Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV may serve as one electrode (e.g., anode) of a TBV capacitor, and the dielectric layer may serve as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor. To that end, in some embodiments, the entire semiconductor layer may comprise a low-resistivity material, whereas in some other embodiments, low-resistivity region(s) may be provided just along the sidewalls local to the TBV, for example, by selective doping in those location(s). In other embodiments, a conductive layer formed between the dielectric layer and the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor.