Multi-chip Package With Through-Chip Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional microelectronic packages face challenges in achieving high bandwidth connections and efficient heat transfer between logic chips and substrates, particularly when other chips are stacked, which can impede thermal performance and increase complexity and cost.
Innovation Solution
A microelectronic package design featuring a substrate with oppositely-facing surfaces, where a logic chip is flip-chip mounted and electrically connected to the substrate, and a memory chip is positioned to partially overlay the rear surface of the logic chip, leaving an uncovered area for a heat spreader, allowing for efficient thermal coupling and high bandwidth connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If another chip is stacked above the logic chip to save space, then the package occupies less surface area, but heat transfer from the logic chip is impeded
Solution Approach 1:
The package structure is segmented into distinct functional zones: a first region containing the logic chip with its own heat dissipation path, and a second region containing the memory chip. This segmentation allows each chip to have dedicated thermal management resources, preventing the memory chip from blocking heat transfer paths of the logic chip.
Solution Approach 2:
The patent transitions from a conventional two-dimensional planar arrangement to a three-dimensional stacked configuration with vertical separation. The logic chip and memory chip are positioned at different vertical levels (z-axis), with the logic chip in a first region and the memory chip in a second region above it. This dimensional change allows both chips to coexist while maintaining independent heat transfer paths to respective heat spreaders.
2Area of stationary object
If another chip is positioned above the logic chip, then space is saved, but the complexity of the package increases
Solution Approach 1:
The patent merges multiple functions into a unified stacked package structure: both the logic chip and memory chip are integrated within the same package footprint, electrical interconnections are established through vertical vias and conductors, and thermal management is provided through integrated heat spreaders. This merging reduces the overall package surface area while maintaining functional independence.
Solution Approach 2:
The memory chip is positioned in a second region that is vertically above and partially overlaps the first region containing the logic chip. This nesting arrangement allows the memory chip to be embedded within the vertical envelope of the package without requiring additional lateral space, effectively placing one component inside the spatial envelope of another.
3Speed
If connections between logic chip and substrate are increased for high bandwidth, then data transfer speed improves, but heat generation increases
Solution Approach 1:
The patent provides localized thermal management by placing dedicated heat spreaders in proximity to each heat-generating component. A first heat spreader is positioned adjacent to the logic chip in the first region, and a second heat spreader is positioned adjacent to the memory chip in the second region. This local quality approach ensures that each chip's heat is dissipated independently and efficiently, preventing heat accumulation despite high-bandwidth operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances thermal performance by maintaining heat transfer efficiency while enabling high bandwidth connections, addressing the complexity and cost issues associated with stacked chip configurations.
Implementation Method 1
enhances thermal performance by maintaining heat transfer efficiency
Implementation Method 2
leaving an uncovered area for a heat spreader, allowing for efficient thermal coupling
Data Source
AI summary
A microelectronic package includes a first microelectronic element comprising logic circuitry which is flip-chip mounted to a substrate, the substrate having terminals for connection with a circuit panel or other external component. A second microelectronic element overlies a rear surface of the first microelectronic element and has contacts electrically coupled with the substrate through electrically conductive interconnects extending through a region of the first microelectronic element. A heat spreader is thermally coupled with the rear surface of the substrate, either directly or through an additional element overlying the rear surface. Additional contacts of the second microelectronic element may be coupled with contacts of the substrate through electrically conductive structure disposed beyond an edge surface of the first microelectronic element.