Through-Chip Via Fuse Cutting in Semiconductor Integrated Circuits

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Solution Overview

Problem

Conventional semiconductor integrated circuits require a separate fuse cutting process, increasing fabrication cost and time, especially when distinguishing between master and slave chips in stack packages.

Innovation Solution

A semiconductor integrated circuit design that includes a through-chip via passing through a conductive pattern and an insulation pattern on its outer circumference to insulate the conductive pattern, allowing the fuse to be cut during the formation of the via, eliminating the need for a separate fuse cutting process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a separate fuse cutting process is used to distinguish master and slave chips, then the chips can be properly identified and controlled, but the fabrication cost and time increase

Engineering Contradiction:
Improvechip identification reliabilityVSAvoidfabrication time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent combines the fuse cutting function with the through-chip via formation process. The via structure is designed to physically interrupt the conductive pattern (fuse) during its formation, eliminating the need for a separate fuse cutting step. This merging of functions directly reduces fabrication time while maintaining chip identification reliability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The conductive pattern (fuse) is pre-positioned in the semiconductor chip at the location where the through-chip via will be formed. This preliminary placement allows the via formation process itself to serve as the fuse cutting mechanism, performing the identification function before final assembly without requiring additional processing steps.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If a separate fuse cutting process is used to distinguish master and slave chips, then the chips can be properly identified and controlled, but the fabrication cost increases

Engineering Contradiction:
Improvechip identification reliabilityVSAvoidfabrication cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the fuse cutting operation with the through-chip via formation operation into a single fabrication step. This consolidation eliminates the need for separate equipment, materials, and process control for fuse cutting, thereby reducing fabrication cost while maintaining the ability to reliably identify master and slave chips.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The through-chip via structure serves multiple functions simultaneously: it provides electrical connection between stacked chips and acts as the fuse-cutting mechanism for chip identification. This multi-functionality reduces the total number of process steps and materials required, lowering overall fabrication cost.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If conventional separate processes are used for via formation and fuse cutting, then each process can be optimized independently, but the overall device complexity increases

Engineering Contradiction:
Improveprocess optimization precisionVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent integrates the fuse cutting function into the via formation process by strategically positioning the conductive pattern within the via formation region. This merging reduces the number of independent process steps from two (via formation + fuse cutting) to one, simplifying the overall fabrication process while maintaining manufacturing precision through coordinated design of the via and conductive pattern.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8563430B2Semiconductor integrated circuit and method for fabricating the same
Publication Date: 2013.10.22 SK HYNIX INC
  • US8563430B2 patent drawing
  • US8563430B2 patent drawing
  • US8563430B2 patent drawing

AI summary

A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via.