Through-Chip Via Power Redistribution for Stacked Memory Die Cooling
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Solution Overview
Problem
The challenge in vertically stacked semiconductor die packages is effective heat dissipation and efficient power distribution, particularly when a high-power logic die is located below the memory die stack, blocking heat sinks and causing voltage drop.
Innovation Solution
A semiconductor structure with continuous through-chip vias (TCVs) extending through multiple memory dies to provide power from a packaging substrate to a logic die located atop the memory die stack, combined with through-silicon vias (TSVs) for power transmission, allowing efficient cooling via a heat sink.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high-power logic die is located below the memory die stack, then the functional capacity of the package is increased, but heat dissipation becomes difficult and voltage drop increases
Solution Approach 1:
The patent inverts the conventional power distribution approach by routing power from the top of the stack downward through through-chip vias, rather than from the bottom upward. This allows the logic die to be positioned at the top where heat can be more effectively dissipated, while still providing power to lower memory dies through the inverted via structure.
Solution Approach 2:
The patent transitions from planar power distribution to three-dimensional vertical power distribution through the stack. Through-chip vias create vertical power pathways that penetrate multiple dies, enabling power delivery in the vertical dimension rather than relying solely on lateral connections at the substrate level.
2Productivity
If a high-power logic die is located below the memory die stack, then the functional capacity of the package is increased, but voltage drop increases
Solution Approach 1:
The inverted via architecture positions the power entry point at the top of the stack, reducing the cumulative resistance path to upper dies. This inversion shortens the current path length compared to bottom-up power distribution, thereby reducing voltage drop across the stack.
Solution Approach 2:
The patent segments the power distribution into multiple independent through-chip via pathways that penetrate individual dies. This segmentation creates parallel current paths, reducing the overall resistance and voltage drop by distributing the current load across multiple separate via channels rather than relying on a single path.
3Quantity of substance
If multiple memory dies are vertically stacked, then the storage capacity is increased without increasing footprint, but the complexity of power distribution increases
Solution Approach 1:
The through-chip via structure serves multiple functions simultaneously: it provides mechanical support between dies, enables signal transmission, and delivers power across die boundaries. This multi-functionality reduces the need for separate dedicated power structures, simplifying the overall power distribution architecture despite the vertical stacking complexity.
Solution Approach 2:
The patent merges power distribution with the mechanical interconnect structure. The same physical via that mechanically bonds multiple dies together also serves as the power conduction pathway, eliminating the need for separate power delivery mechanisms and reducing overall system complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables effective power delivery and cooling of the logic die, independent of the number of memory dies, with reduced resistance and facilitated heat dissipation, enabling practical implementation and testing of known good stacks.
Implementation Method 1
The location of the logic die atop the plurality of memory dies allows more efficient cooling of the logic die via a heat sink
Data Source
AI summary
A semiconductor structure that includes a plurality of memory dies in a stacked configuration, and at least one through-chip via (TCV) that extends through the plurality of memory dies where the at least one TCV is adapted to provide power to the plurality of memory dies.