Through-Chip Vias in Semiconductor Wafers
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Solution Overview
Problem
The high cost and risk of damaging devices when forming through-chip electrical connections on fully processed chips, as well as the inefficiency in conventional methods that do not allow for precise alignment and may result in unusable chips if errors occur.
Innovation Solution
Forming through-chip connections on either a blank wafer before device creation or on partially processed wafers before back-end processing, allowing for precise placement and conductivity without risking damage to existing devices, and enabling the formation of sensitive transistors in defect-free areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-chip connections are formed on fully processed chips, then electrical connections through the chip are achieved, but the risk of damaging devices and the cost increase significantly worsen
Solution Approach 1:
The patent applies preliminary action by forming through-chip connections on a blank wafer before any devices are created, or on a partially processed wafer before back-end processing. This allows the connections to be established in advance, eliminating the risk of damaging finished devices while still achieving the desired electrical connectivity through the chip.
2Manufacturing precision
If through-chip vias are formed near devices on fully processed chips, then electrical connections are achieved, but alignment errors can damage devices or metallization layers
Solution Approach 1:
The patent forms through-chip connections on a blank wafer or partially processed wafer before devices are fully created. This preliminary timing allows alignment to be established on a simpler substrate without the complexity of finished devices, thereby improving alignment precision and eliminating the risk of damaging sensitive devices or metallization layers.
3Adaptability or versatility
If through-chip connections are formed on fully processed chips, then routing connections are achieved, but the chip cost increases significantly
Solution Approach 1:
The patent establishes through-chip connections on a blank wafer or partially processed wafer before back-end processing. This timing allows the connections to be formed when the wafer is still relatively simple and inexpensive to work with, thereby achieving the desired routing capability while significantly reducing the manufacturing cost compared to forming connections on fully processed chips.
4Reliability
If back-end processing is completed before forming through-chip connections, then device functionality is achieved, but sensitive transistors are exposed to contamination risk
Solution Approach 1:
The patent forms through-chip connections on a blank wafer or partially processed wafer before back-end processing is completed. This preliminary timing allows sensitive transistors to be formed in defect-free areas without exposure to contamination from subsequent via formation and filling processes, thereby improving transistor reliability while still enabling through-chip routing.
Data Source
AI summary
A method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and performing back-end processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a metallization layer. An alternative method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a conductive semiconductor layer.