Through-Core Via Substrate for Low-Latency Package Interconnects
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Solution Overview
Problem
Current methods for connecting semiconductor device packages face challenges in achieving close electrical connections when z-height is constrained, leading to thermal, electrical, and routing issues, particularly in side-by-side configurations where space is available but not utilized effectively.
Innovation Solution
A substrate with a portion having an exposed core layer and vias that expose a conductive layer, allowing for direct electrical connection between semiconductor device packages without needing to route signals through a motherboard, thereby reducing z-height and enhancing communication efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If semiconductor device packages are connected side-by-side on a motherboard, then space utilization is improved, but electrical connection distance increases causing signal delays
Solution Approach 1:
The patent introduces an interposer substrate as an intermediary component between adjacent semiconductor device packages. This interposer contains through-silicon vias (TSVs) that provide direct vertical electrical interconnects, allowing packages to communicate through the interposer rather than routing signals through the motherboard. The interposer acts as a mediator that reduces signal path length while maintaining compact side-by-side packaging.
Solution Approach 2:
The patent transitions from planar two-dimensional packaging to three-dimensional vertical interconnection by implementing through-silicon vias that extend vertically through the interposer substrate. This dimensional change allows electrical connections to be made in the vertical dimension rather than relying on long horizontal traces across the motherboard, thereby reducing signal delay while maintaining compact footprint.
2Productivity
If through-silicon vias are implemented in the interposer, then electrical connection efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action by forming through-silicon vias and copper fills in the interposer substrate before mounting the semiconductor device packages. This pre-fabrication approach allows complex TSV structures to be prepared in advance, simplifying the subsequent assembly process and reducing overall manufacturing complexity despite the advanced techniques required.
Solution Approach 2:
The interposer substrate serves multiple functions: it provides mechanical support for mounting packages, establishes electrical interconnections through TSVs, and enables thermal management. This multi-functionality consolidates several requirements into a single component, reducing overall system complexity despite the sophisticated TSV fabrication process.
3Area of stationary object
If packages are stacked vertically to reduce footprint, then area is reduced, but z-height increases causing thermal and routing issues
Solution Approach 1:
The patent redistributes thermal management resources in the vertical dimension by incorporating thermal vias and heat dissipation structures within the interposer substrate. This allows heat from vertically stacked packages to be conducted away through the interposer's thermal pathways, managing thermal issues that would otherwise result from increased z-height in stacked configurations.
Data Source
AI summary
A package substrate for connecting together semiconductor devices with other semiconductor device packages. The package substrate includes an exposed core layer with at least one via exposing a conductive layer of the package substrate. A first portion of the package substrate may include a solder mask on top and bottom surfaces. A first semiconductor device may be connected to the first portion of the package substrate. Layers of a second portion of the package substrate are removed to expose a core layer and vias are created in the exposed core layer to expose the conductive layer. Conducive material at least partially filling the vias may be used to connect a semiconductor device package to the second portion of the package substrate. The semiconductor device packages may communicate through conductive layers in the package substrate. The package substrate may be used to connect the semiconductor packages to a motherboard.