Through-Die Capacitor Structure for High-Capacitance IC Stacking
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in achieving high capacitance values without significantly increasing the IC footprint, as large capacitors require substantial area, thereby increasing costs and reducing design flexibility.
Innovation Solution
A semiconductor structure is formed by arranging a capacitor structure that extends through neighboring interconnection structures of different dies, utilizing a trench to integrate the capacitor across multiple substrates, allowing for high capacitance with a reduced footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MIM/MOM capacitors are integrated within a single die to achieve high capacitance values, then the capacitance requirement is met, but the IC area increases significantly leading to higher costs
Solution Approach 1:
The capacitor structure is segmented across multiple dies, with each die containing a portion of the total capacitance. The first die includes a first capacitor and the second die includes a second capacitor, which are electrically connected to achieve the total required capacitance value without concentrating all capacitive elements in a single large die.
Solution Approach 2:
The solution transitions from a two-dimensional planar integration within a single die to a three-dimensional multi-die stacking architecture. By bonding multiple dies together vertically, the patent achieves high capacitance values while maintaining a compact footprint, effectively utilizing the vertical dimension to increase functional density.
2Area of stationary object
If capacitor area is reduced to maintain small IC footprint, then area efficiency is improved, but manufacturing complexity increases due to advanced integration requirements
Solution Approach 1:
The complex capacitor integration is segmented into separate, standardized units on different dies. Each die can be manufactured independently with standard processes, and the capacitors are connected through controlled inter-die vias and conductive structures, reducing overall manufacturing complexity compared to integrating all capacitors in a single complex die.
Solution Approach 2:
The multi-die architecture with standardized bonding interfaces and interconnection structures creates a universal platform that can be applied to various capacitor designs and configurations. The same inter-die connection methodology can be used across different product families, reducing process development complexity.
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a first die and a second die. The first die includes a substrate, an interconnection structure and a capacitor structure. The substrate has a front-side surface and a back-side surface. The interconnection structure is disposed over the front-side surface. The capacitor structure extends from the back-side surface to the front-side surface and into the interconnection structure. The second die is disposed over the back-side surface and is bonded to the first die. A method for forming a semiconductor structure is also provided.