Through-Die Vias for Compact IC Stacking and Signal Bypass
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Solution Overview
Problem
The handling and implementation of small, thin integrated circuit dies during manufacturing and testing are challenging due to damage risks, and the increasing density of electronic devices on silicon wafers complicates the manufacturing process, particularly in achieving efficient electrical access and coupling to various types of circuitry.
Innovation Solution
The integration of vias through the dies, along with electrical contacts on both surfaces, allows for the coupling of stacked circuits and provides an electrical signal path that bypasses the integrated circuit, enabling compact stacking and signal coupling to both the die and external circuitry, facilitated by wafer-level chip scale packaging techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of electronic devices per given area of the silicon wafer is increased, then the productivity is improved, but the manufacturing precision deteriorates due to increased difficulty in handling and processing
Solution Approach 1:
The patent divides the wafer into multiple individual dies with separate processing zones. Each die is isolated by trenches that allow independent handling and processing, enabling high-density wafer fabrication while maintaining precise control over each individual die during manufacturing and testing operations
Solution Approach 2:
The patent introduces intermediary structures including support frames, trenches, and isolation regions between dies. These intermediary elements facilitate handling of individual dies while maintaining overall wafer integrity, allowing increased device density without compromising manufacturing precision during testing and processing operations
2Volume of moving object
If small, thin integrated circuit dies are used, then the volume is reduced, but the reliability deteriorates due to damage risks during handling and testing
Solution Approach 1:
The patent provides beforehand support structures and handling mechanisms for small, thin dies. Support frames and protective configurations are established prior to handling and testing operations, cushioning the fragile dies against damage while enabling their compact size and high-density integration
Solution Approach 2:
The patent employs thin film structures and flexible support configurations that accommodate the small, thin die geometry. These thin film and flexible support structures provide necessary mechanical support during handling and testing while maintaining the compact die size required for high-density integration
3Adaptability or versatility
If electrical access is provided through the dies, then the adaptability is improved for coupling to various circuitry, but the device complexity increases due to additional via and contact structures
Solution Approach 1:
The patent implements universal electrical access structures through standardized via and contact configurations that can couple to various types of circuitry. The through-die via structures serve multiple functions including electrical connection, mechanical support, and alignment features, enabling adaptable coupling to different circuit configurations without proportionally increasing complexity
Solution Approach 2:
The patent merges multiple functions into integrated via and contact structures. The electrical access structures simultaneously provide electrical connection, mechanical support, and alignment functionality, reducing the number of separate components needed and thereby limiting the increase in device complexity while achieving high adaptability for coupling to various circuitry
Data Source
AI summary
Aspects of the disclosure are directed to integrated circuit dies and their manufacture. In accordance with one or more embodiments, a plurality of integrated circuit dies are provided in a semiconductor wafer, with each integrated circuit die having: an integrated circuit within the die, a via extending from a first surface to a second surface that opposes the first surface, and first and second electrical contacts at the first surface respectively coupled to the via and to the integrated circuit. Lanes are created in a front side of the wafer between the dies, and a portion of the back side of the wafer is removed to expose the lanes. A further contact and/or via is also exposed at the backside, with the via providing an electrical signal path for coupling electrical signals through the integrated circuit die (e.g., bypassing circuitry therein).


