Through-Dielectric Via Structure With Metal Stub Alignment
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Solution Overview
Problem
The challenge in semiconductor manufacturing is creating through dielectric vias that connect backside power distribution networks with metal levels in the BEOL region without punching through metal lines, as the via width is often larger than the metal lines it needs to connect.
Innovation Solution
A semiconductor structure is formed with a metal stub above a transistor, where a through dielectric via is embedded, and its top portion is partially embedded in the metal stub, ensuring alignment and sufficient width to prevent punching through, with the metal stub's width being significantly larger than the metal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a through dielectric via is created with a width larger than the metal line it connects, then connectivity and current carrying capacity are improved, but the risk of punching through the metal line increases
Solution Approach 1:
The via structure is segmented into two parts: a first via portion extending from the backside contact through the substrate, and a second via portion extending from the metal line down to embed in the first via portion. This segmentation allows each via portion to be optimized independently - the first portion can be wider for better connectivity while the second portion is precisely aligned to connect to the metal line without punching through it.
Solution Approach 2:
The first via portion acts as an intermediary element between the backside contact and the metal line. It provides a transition zone that allows the via to achieve sufficient width for good connectivity while the second via portion maintains precise alignment to avoid damaging the metal line during formation.
2Reliability
If the via width is increased to reduce contact resistance, then electrical connectivity is improved, but the difficulty of avoiding metal line damage during via formation increases
Solution Approach 1:
The via formation process is segmented into separate steps for creating the first via portion (with larger width for low resistance) and the second via portion (with precise alignment to metal line). This allows each portion to be optimized for its specific function without compromising the other.
Solution Approach 2:
The first via portion is formed in advance with a larger width to ensure low contact resistance. Subsequently, the second via portion is formed with precise alignment to the metal line. This preliminary action of creating the wider first portion before forming the second portion simplifies the overall manufacturing process.
Data Source
AI summary
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first area having a back-end-of-line (BEOL) region that includes a first set of vias; a metal level with one metal line above the first set of vias; and a second set of vias above the metal level; and a second area having a metal stub, where a bottom surface of the metal stub is substantially aligned with a bottom surface of the first set of vias and a top surface of the metal stub is substantially aligned with either a top surface of the one metal line of the metal level or a top surface of the second set of vias, and where the metal stub has a horizontal width that is at least 10 times larger than a width of the one metal line. A method of forming the semiconductor structure is also provided.