Through-Dielectric Via Structures for Semiconductor Die Stacking
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Solution Overview
Problem
Current methods for stacking semiconductor dies in three-dimensional memory devices face challenges in efficiently bonding multiple memory dies to a support chip while maintaining effective vertical interconnection and high bit density without the need for expensive through-substrate vias.
Innovation Solution
A bonded assembly is formed by bonding a memory die with a support die, where the memory die includes a three-dimensional memory device with alternating stacks of insulating and conductive layers, and metal interconnect structures that pass through dielectric material portions to connect bonding pads without contacting semiconductor material, enabling scalable stacking and independent control of word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-substrate vias are used for vertical interconnection, then reliable electrical connection is achieved, but manufacturing cost increases significantly
Solution Approach 1:
The invention extracts the interconnection function from the substrate itself and relocates it to the die level. Through-die vias are formed in the dielectric layers of each memory die, allowing vertical interconnection without requiring expensive through-substrate vias in the support chip. This separates the interconnection function from the substrate, reducing manufacturing cost while maintaining reliability.
Solution Approach 2:
The invention transitions from planar interconnection to vertical interconnection by forming through-die via structures that extend through the dielectric layers in the vertical dimension. This three-dimensional via structure enables electrical connection between bonding pads on opposite sides of each die, providing reliable vertical interconnection without substrate penetration.
2Quantity of substance
If multiple memory dies are stacked to increase bit density, then storage capacity improves, but bonding complexity and difficulty increase
Solution Approach 1:
The invention segments the memory system into multiple independent memory dies that can be manufactured separately and then stacked. Each die contains a complete three-dimensional memory structure with alternating conductive and insulating layers, allowing independent fabrication and testing before bonding to the support chip and each other, thereby reducing overall bonding complexity.
Solution Approach 2:
The invention performs preliminary actions by forming through-die via structures and bonding pads on each memory die before stacking. The dielectric layers are prepared with embedded via structures that protrude from the die surfaces, and bonding pads are pre-configured to match the support chip and adjacent dies, simplifying the actual bonding process and reducing complexity.
3Ease of manufacture
If conventional bonding methods are used, then manufacturing process is simple, but vertical interconnection effectiveness is reduced
Solution Approach 1:
The invention enhances vertical interconnection by creating three-dimensional via structures that extend through the dielectric layers and protrude from the die surfaces. These via structures provide direct vertical electrical pathways between bonding pads on opposite sides of each die, significantly improving interconnection effectiveness while maintaining compatibility with conventional bonding processes.
Solution Approach 2:
The invention implements nested structures where conductive via structures are embedded within dielectric material layers. The via structures are nested within the dielectric layers and extend to the die surfaces, creating a hierarchical structure that provides effective vertical interconnection while maintaining manufacturing simplicity.
Data Source
AI summary
Memory dies configured for multi-stacking within a bonded assembly may be provided without using through-substrate vias that extend through semiconductor substrates. A first memory die may be provided by forming interconnect-side bonding pads on a three-dimensional memory device that overlies a semiconductor substrate. A support die including a peripheral circuitry is boned to the interconnect-side bonding pads. The semiconductor substrate is removed, and array-side bonding pads are formed on an opposite side of the interconnect-side bonding pads. Electrically conductive paths that do not pass through any semiconductor material portion are formed between the interconnect-side bonding pads and the array-side bonding pads, thereby avoiding costly formation of through-substrate via structures that extend through any semiconductor substrate. A second memory die may be bonded to the first memory die to provide stacking of multiple memory dies. Semiconductor substrates may be removed from each memory die upon bonding to a pre-existing assembly.