Through-Dielectric Vias for 3D Memory Parasitic Capacitance
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Solution Overview
Problem
Three-dimensional (3D) memory devices with through-silicon vias (TSVs) face challenges due to parasitic capacitance and poor isolation between semiconductor substrates and TSVs, which affect data reliability, memory access speed, and chip size, especially when stacking multiple semiconductor chips require precise processing.
Innovation Solution
The use of through-dielectric vias (TDVs) with a larger width and shallow trench isolation (STI) regions reduces parasitic capacitance and allows for more precise stacking, enabling smaller chip sizes and higher memory access speeds by using conductive plugs with a barrier portion and conductive portion configuration, and a dielectric film to insulate adjacent device regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are used to interconnect stacked semiconductor chips, then vertical interconnection and 3D memory capacity are improved, but parasitic capacitance increases and isolation between substrates deteriorates
Solution Approach 1:
The patent introduces TDVs (through-dielectric vias) as intermediary structures between TSVs and semiconductor substrates. These TDVs are formed in dielectric films covering the substrates, creating an isolated conductive path that mediates the connection while preventing direct parasitic coupling between the TSV and substrate, thus reducing parasitic capacitance while maintaining vertical interconnection functionality
Solution Approach 2:
The patent segments the original TSV structure into multiple components: the TSV itself, the dielectric film layers, and the TDVs formed in these dielectric films. This segmentation isolates the conductive elements from direct substrate contact, reducing parasitic effects while preserving the vertical interconnection function across stacked chips
2Quantity of substance
If a large number of semiconductor chips are stacked to increase memory capacity, then memory capacity and bandwidth are improved, but manufacturing precision requirements increase due to TSV length relative to chip thickness
Solution Approach 1:
The dielectric films and TDVs act as intermediary layers that facilitate precise alignment during stacking. The TDVs provide defined conductive contact points through the dielectric films, serving as alignment references that enable accurate positioning of stacked chips, thereby reducing stacking precision requirements despite increased chip counts
Solution Approach 2:
The dielectric films are formed on the semiconductor substrates before stacking, preliminarily establishing the TDV structures and alignment features. This preliminary preparation of isolation and conductive structures enables subsequent precise stacking operations by providing pre-defined alignment references and reducing sensitivity to positioning errors
3Productivity
If TSVs are used for vertical interconnection, then 3D memory structure and bandwidth are improved, but chip size reduction is limited due to processing precision constraints
Solution Approach 1:
The TDVs in dielectric films serve as compact intermediary structures that enable vertical interconnection with reduced lateral footprint compared to traditional TSV approaches. This mediator structure allows for smaller chip sizes while maintaining high-speed vertical data transfer capabilities through the isolated conductive paths
Data Source
AI summary
Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming a plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs.