Through Electrode Air Gap Structure for Parasitic Capacitance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-stacked semiconductor devices, parasitic capacitance introduced by through electrodes hinders signal integrity at high frequencies, necessitating a solution to minimize this capacitance.
Innovation Solution
The semiconductor device incorporates an insulation layer structure with an air gap between silicon oxide or carbon-doped silicon oxide layers, and a through electrode made of copper or tungsten, with a barrier layer and a sacrificial layer pattern formed using hydrocarbon-based materials, which is removed using UV radiation to create a structure that reduces parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a through electrode is used to interconnect vertically stacked semiconductor chips, then electrical connection between chips is achieved, but parasitic capacitance is introduced that degrades signal integrity at high frequencies
Solution Approach 1:
The via hole is divided into multiple sections by inserting insulation layers at different depths, creating segmented conductive paths that reduce parasitic capacitance while maintaining electrical connectivity between stacked chips
Solution Approach 2:
Insulation layers are introduced as intermediary elements within the via hole structure, positioned between conductive components to reduce capacitive coupling and minimize parasitic effects on signal integrity
2Reliability
If insulation layers are added to reduce parasitic capacitance, then signal integrity improves, but device structure and manufacturing complexity increase
Solution Approach 1:
Insulation layers are selectively positioned at specific depths within the via hole rather than uniformly throughout, optimizing parasitic capacitance reduction while minimizing unnecessary structural complexity
Solution Approach 2:
The dielectric constant parameter is changed by introducing low-k insulation materials at strategic locations within the via hole, reducing parasitic capacitance without requiring complex multi-layer structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The air gap structure effectively minimizes parasitic capacitance, enhancing signal integrity at high frequencies and improving the performance of multi-stacked semiconductor devices.
Implementation Method 1
The step of removing the sacrificial layer pattern is performed by an ultraviolet (UV) radiation process with a thermal treatment or an electron beam radiation process for vaporizing the sacrificial layer pattern
Implementation Method 2
The UV radiation process is performed using a light source having a wavelength of about 200 nm to about 350 nm at a temperature of about 300° C. to about 500° C.
Implementation Method 3
the parasitic capacitance introduced by the through electrode is required to be minimized
Implementation Method 4
The step of removing the sacrificial layer pattern is performed by an ultraviolet (UV) radiation process with a thermal treatment or an electron beam radiation process for vaporizing the sacrificial layer pattern
Data Source
AI summary
A semiconductor device comprises a top surface having a first contact, a bottom surface having a second contact, a via hole penetrating a substrate, an insulation layer structure on a sidewall of the via hole, the insulation layer structure having an air gap therein, a through electrode having an upper surface and a lower surface on the insulation layer structure, the through electrode filling the via hole and the lower surface being the second contact, and a metal wiring electrically connected to the upper surface of the through electrode and electrically connected to the first contact.