Through-Electrode Test Circuit for Cell-Array-Free Die Screening
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Solution Overview
Problem
Testing integrated circuit chips without a cell array is challenging due to the difficulty in generating various patterns of data needed for testing, especially for base dies in 3D stacked memory devices, which can lead to late detection of defects and increased waste.
Innovation Solution
Incorporating a repair circuit with a selection signal generation circuit and transmission circuits that allow for toggling data signals through through-silicon vias or through electrodes, enabling wafer-level testing and identification of defective electrodes, even in the absence of a cell array, by generating test signals and switching data paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If wafer level testing is performed on integrated circuit chips without a cell array, then early defect detection and waste reduction are achieved, but the ability to generate various test data patterns becomes difficult
Solution Approach 1:
The patent applies preliminary action by performing wafer-level testing before the chips are stacked into 3D packages. This allows defect detection to occur at an earlier stage when individual chips are still accessible and can be tested independently, avoiding the need to disassemble completed 3D packages for testing.
Solution Approach 2:
The patent introduces an intermediary test data generation circuit within the base die that synthesizes test patterns without requiring a cell array. This intermediary component enables the generation of diverse test data sequences by using shift registers and logic circuits to create pseudorandom patterns, thereby solving the limitation of testing chips without traditional memory structures.
2Loss of substance
If individual die testing is performed before stacking in 3D packages, then waste is reduced by identifying defective dies early, but the complexity of test signal transmission through through-silicon vias increases
Solution Approach 1:
The patent performs testing at the wafer level before the through-silicon vias are formed and before stacking occurs. This preliminary testing approach allows defect identification while the test signal paths are still accessible on the wafer surface, avoiding the complexity of transmitting test signals through the newly formed through-silicon vias that would be required if testing occurred after stacking.
Solution Approach 2:
The patent extracts the testing function from the final packaged product and performs it separately at the wafer level. By separating the testing operation from the completed 3D package structure, the system can test individual dies using simplified signal paths on the wafer without requiring the complex through-silicon via infrastructure that will be added later during packaging.
3Speed
If through electrodes are used for vertical interconnection in 3D packages, then signal transfer speed and bandwidth are improved, but the difficulty of detecting defective electrodes increases
Solution Approach 1:
The patent performs testing before the through-silicon vias are formed, allowing detection of potential via defects during the wafer processing stage. By testing at this preliminary stage, the system can identify electrodes or vias that will be defective before they are created, avoiding the need to detect defects through the completed vertical interconnection structure.
Solution Approach 2:
The patent implements beforehand cushioning by incorporating redundant through-silicon vias and repair circuits that can compensate for defective electrodes. The system is designed with built-in redundancy before the stacking process, allowing defective vias to be detected and bypassed using alternative pathways, thereby cushioning against the impact of electrode defects on overall system performance.
Data Source
AI summary
An integrated circuit chip includes a first through electrode and a second through electrode formed through the integrated circuit chip, a transmission circuit suitable for selecting one of signals transmitted through the first and second through electrodes, respectively, and transmitting the selected signal to a data line, in response to a selection signal, and a selection signal generation circuit suitable for generating the selection signal by toggling the selection signal, during a test operation.