Through-Electrode Dummy Gate Layout for CMP Yield Stability
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Solution Overview
Problem
Conventional semiconductor devices with through electrodes face yield deterioration due to excessive polishing during chemical mechanical polishing (CMP), which affects the flatness of interlayer insulating films and wiring layer formation.
Innovation Solution
A semiconductor device with a through electrode covered by an insulating film, featuring a dummy gate disposed between the outer and inner peripheries of the insulating film, which acts as a CMP stopper to prevent excessive polishing and improve yield, and can be made from materials like polycrystalline silicon, tungsten, or silicon nitride.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If no dummy pattern is formed in the through electrode formation portion, then notch generation in the side wall of the through electrode is suppressed, but excessive polishing during CMP deteriorates the flatness of the interlayer insulating film
Solution Approach 1:
A dummy gate structure is introduced as an intermediary element between the through electrode formation portion and the interlayer insulating film. This dummy gate serves as a mediator that prevents excessive polishing of the interlayer insulating film during CMP while not interfering with the through electrode formation process, thereby resolving the contradiction between suppressing notch generation and maintaining flatness
Solution Approach 2:
The dummy gate is formed in advance before the interlayer insulating film deposition and CMP processes. By preliminarily placing the dummy gate in the through electrode formation portion, the structure prepares a protective element that will prevent excessive polishing during subsequent CMP steps, while not affecting the through electrode side wall formation
2Reliability
If dummy pattern is formed avoiding the inside of the insulating film, then notch generation is suppressed, but excessive polishing during CMP deteriorates the flatness and yield
Solution Approach 1:
The dummy gate acts as an intermediary structure placed within the insulating film covering the through electrode. It mediates between the need for high yield (by suppressing notch generation) and the need for flatness (by preventing excessive CMP polishing), allowing both requirements to be satisfied simultaneously
Solution Approach 2:
The dummy gate is specifically positioned in the through electrode formation portion, creating a localized quality change in the insulating film structure. This local placement ensures that the protective effect against excessive polishing is concentrated where needed (in the through electrode formation area) without affecting other regions of the interlayer insulating film
Data Source
AI summary
A yield is improved in a semiconductor device in which a through electrode covered with an insulating film is formed. A semiconductor device includes a through electrode, an insulating film, and a wiring layer. In a semiconductor device including a through electrode, an insulating film, and a wiring layer, the through electrode penetrates the semiconductor substrate along a direction perpendicular to a predetermined front surface of the semiconductor substrate. Furthermore, the insulating film covers the through electrode. Moreover, the wiring layer includes a dummy gate disposed in a region between an outer periphery of the insulating film and an inner periphery of the insulating film on the front surface.