Through-Electrode Structure With Etch Delay Layer for 3D Packages
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Solution Overview
Problem
The development of 3D semiconductor packages requires technologies that can form through electrodes with excellent reliability and reproducibility, as existing methods face challenges in achieving consistent electrical connections and preventing defects such as pad open defects due to differences in etching depths caused by varying through electrode widths.
Innovation Solution
The semiconductor device incorporates an etching delay layer with a lower etching rate than the substrate material, strategically placed between the substrate and interlayer insulating film, to reduce the difference in etching depths and prevent defects, while also featuring tapered end portions in the through electrodes to optimize electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If through electrodes of different widths are formed in the substrate, then the electrical connection requirements for different circuits are satisfied, but the etching depths differ causing pad open defects and reduced reliability
Solution Approach 1:
The patent applies local quality by forming an etching delay layer selectively in specific regions where wider through electrodes are to be formed. This layer has different etching characteristics than the surrounding substrate, causing the etching process to proceed at different rates in different regions. As a result, through electrodes of different widths can be formed with consistent depths, preventing pad open defects while maintaining the ability to satisfy different electrical connection requirements.
2Ease of manufacture
If conventional etching methods are used without etching delay layer, then the manufacturing process is simple, but pad open defects occur due to inconsistent etching depths
Solution Approach 1:
The etching delay layer acts as an intermediary element between the substrate regions requiring different etching depths. This intermediate layer modifies the etching process locally, allowing the formation of through electrodes with consistent depths despite width variations. The delay layer is temporarily present during etching and can be removed subsequently, thus maintaining manufacturing simplicity while dramatically improving reliability by preventing pad open defects.
3Manufacturing precision
If through electrodes with uniform width are formed, then etching depth consistency is maintained, but the ability to meet different electrical connection requirements is limited
Solution Approach 1:
By introducing the etching delay layer selectively in specific regions, the patent enables local modification of etching characteristics. This allows through electrodes of different widths to be formed in different regions while maintaining consistent etching depths. The local quality approach thus preserves manufacturing precision while simultaneously enabling adaptability to meet diverse electrical connection requirements for different circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and reproducibility of through electrodes by minimizing defects and ensuring consistent etching depths, thereby improving the overall performance and reliability of 3D semiconductor packages.
Implementation Method 1
an etching delay layer with a lower etching rate than the substrate material, strategically placed between the substrate and interlayer insulating film, to reduce the difference in etching depths
Data Source
AI summary
A semiconductor device, includes: a substrate having a first surface on which a plurality of devices are disposed and a second surface, opposite to the first surface; an interlayer insulating film on the first surface of the substrate; an etching delay layer disposed in a region between the substrate and the interlayer insulating film; first and second landing pads on the interlayer insulating film; a first through electrode penetrating through the substrate and the interlayer insulating film; and a second through electrode penetrating the substrate, the etching delay layer, and the interlayer insulating film, the second through electrode having a width, greater than that of the first through electrode, wherein each of the first and second through electrodes includes first and second tapered end portions in the interlayer insulating film, each of first and second tapered end portions having a cross-sectional shape narrowing closer to the landing pads.