Through-Electrode Fabrication Without Carrier Handling
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Solution Overview
Problem
The existing methods for fabricating semiconductor devices with through-electrodes face challenges such as high costs due to the use of carriers, difficulty in aligning through-electrodes, and complex handling processes, especially during the thinning of semiconductor wafers.
Innovation Solution
A semiconductor device and method for fabricating through-electrodes that allow for stacking without a carrier, enabling easy handling and alignment of through-electrodes, where the wafers are thinned and through-electrodes are formed after thinning, eliminating the need for separate carriers and simplifying the process by using conductive interconnections with L-shaped pads and through-electrodes that penetrate adhesive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a carrier is used for handling thinned wafers, then ease of operation is improved, but device complexity and cost increase due to attaching/detaching requirements
Solution Approach 1:
The invention extracts and eliminates the carrier from the wafer handling process. By maintaining the wafer at its original thickness during through-electrode formation, the need for carrier attachment and detachment is completely removed, simplifying the process while maintaining ease of operation.
Solution Approach 2:
Instead of thinning the wafer first and then using a carrier for handling (conventional approach), the invention inverts the sequence by forming through-electrodes in the original-thickness wafer first, then thinning afterward. This eliminates the carrier requirement entirely.
2Ease of operation
If a carrier is used for wafer handling, then ease of operation is improved, but manufacturing cost increases
Solution Approach 1:
The carrier is extracted from the manufacturing process. By forming through-electrodes before thinning, the expensive carrier attachment/detachment operations are eliminated, directly reducing manufacturing costs while maintaining operational ease through alternative handling methods.
Solution Approach 2:
The invention replaces the expensive, reusable carrier with a simpler, disposable approach where wafers are handled in their original thickness state through-electrode formation, eliminating the need for costly carrier infrastructure.
3Manufacturing precision
If through-electrodes are formed in thinned wafers, then alignment precision may be improved, but device complexity increases due to carrier requirements
Solution Approach 1:
The invention inverts the conventional sequence by forming through-electrodes in original-thickness wafers before thinning. This eliminates carrier complexity while maintaining alignment precision through alternative positioning methods described in the patent.
Solution Approach 2:
Through-electrodes are formed in advance while the wafer is still at its original thickness, which provides better mechanical stability and alignment reference surfaces. The thinning operation is performed afterward, preserving the alignment already achieved during through-electrode formation.
4Ease of manufacture
If wafers are thinned before through-electrode formation, then ease of manufacture is improved, but ease of operation worsens due to handling difficulties
Solution Approach 1:
The invention inverts the conventional sequence by forming through-electrodes before thinning the wafer. This maintains wafer mechanical strength during through-electrode formation, making the process easier to manufacture, while eliminating the need for complex carrier handling of thinned wafers.
Data Source
AI summary
A semiconductor device having through-electrodes and methods for fabricating the same are provided. The semiconductor device may include a first semiconductor chip including a first active surface on which a first top pad is provided; a second semiconductor chip including a second active surface on which a second top pad is provided and a second inactive surface on which a second bottom pad is provided, the second semiconductor chip being stacked on the first semiconductor chip with the second active surface facing the first active surface; and a conductive interconnection configured to electrically connect the chips. The conductive interconnection includes a first through-electrode that penetrates the second semiconductor chip and electrically connects the second bottom pad to the second top pad; and a second through-electrode that passes through the second top pad without contacting the second top pad, and electrically connects the second bottom pad to the first top pad.


