Through-Electrode Pad Structure for Misalignment and Via Void Reduction
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Solution Overview
Problem
Semiconductor devices face challenges with misalignment of pads and increased occurrence of voids in vias, which affect their reliability and performance.
Innovation Solution
A semiconductor device design featuring a first pad, a through electrode, an upper passivation layer, and a second pad with an upper barrier layer, where the second pad extends into the passivation layer and is electrically connected to the through electrode, using different materials for the pads and electrodes to reduce misalignment and voids, and a method of fabrication that includes forming a via hole, a through electrode, and a recess region with specific deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional pad and via structures are used, then fabrication is simpler, but pad misalignment and voids in vias occur reducing reliability
Solution Approach 1:
The pad structure is segmented into multiple parts: a first pad in the first dielectric layer, a second pad extending into the upper passivation layer, and intermediate structures including via holes and barrier layers. This segmentation allows for better alignment control and reduced void formation in each segment, thereby improving overall reliability.
Solution Approach 2:
The upper barrier layer is formed in advance on the inner surface of the recess region before the second pad is formed. This preliminary action ensures proper adhesion and prevents void formation in the via region, improving reliability without significantly complicating the overall fabrication process.
2Manufacturing precision
If pads are made larger to reduce misalignment, then alignment tolerance increases, but device area increases
Solution Approach 1:
The second pad extends vertically into the upper passivation layer, utilizing the vertical dimension to improve alignment precision. This allows the pad to maintain smaller horizontal dimensions while achieving better alignment tolerance through its three-dimensional structure, thus avoiding increase in device area.
3Reliability
If via holes are filled completely to avoid voids, then material consumption increases, but fabrication cost increases
Solution Approach 1:
The upper barrier layer is applied locally on the inner surface of the recess region rather than uniformly filling the entire via hole. This local application ensures proper adhesion and prevents void formation at critical interfaces while minimizing material consumption, thereby improving reliability without significantly increasing material usage.
Data Source
AI summary
Disclosed are semiconductor devices and methods of fabricating the same. The semiconductor device includes a first dielectric layer including a first pad, a second dielectric layer on the first dielectric layer, a through electrode that penetrates the second dielectric layer and is electrically connected to the first pad, an upper passivation layer on the second dielectric layer, a second pad on the upper passivation layer, and an upper barrier layer between the upper passivation layer and the second pad. The first pad and the through electrode include a first material. The second pad includes a second material that is different from the first material of the first pad and the through electrode. The second pad includes a first part on the upper passivation layer, and a second part that extends from the first part into the upper passivation layer and is connected to the through electrode.