Through Electrode Passivation for Stacked Semiconductor Packages
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Solution Overview
Problem
The multi-chip packaging technique for semiconductor devices faces challenges in providing sufficient space for electrical connections between semiconductor chips, limiting the performance and storage capacity of semiconductor packages.
Innovation Solution
The use of through electrodes with protrusions and a passivation pattern having different etch selectivity layers, along with front-side and back-side bumps, to enhance electrical connections and increase the height of back-side bumps for improved stacking and connection efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are assembled in a single package to increase storage capacity, then the data storage capacity is improved, but the space for electrical connections between chips becomes insufficient
Solution Approach 1:
The patent transitions from planar chip arrangement to vertical stacking by forming through electrodes that penetrate the substrate thickness direction. This three-dimensional configuration allows multiple chips to be stacked vertically, dramatically increasing storage capacity while maintaining adequate connection space through the vertical dimension rather than competing for horizontal area.
Solution Approach 2:
The substrate is divided into multiple through electrodes distributed across the chip, with each through electrode providing independent electrical connection pathways. This segmentation allows multiple parallel connection channels, increasing the total connection capacity while maintaining compact packaging.
2Reliability
If through electrodes are formed to penetrate multiple chips at wafer level for better connection, then electrical and physical connection between chips is improved, but the manufacturing complexity increases
Solution Approach 1:
Through electrodes are formed at the wafer level before chip dicing and packaging. This preliminary formation of connection structures allows subsequent chip stacking and bonding to proceed more easily, as the electrical pathways are already established. The through electrodes are created while the wafer is still in a manageable state, avoiding the need to form connections after individual chips are separated.
Solution Approach 2:
The through electrodes serve multiple functions: providing electrical connection pathways, acting as mechanical support structures for stacked chips, and enabling both signal transmission and power delivery. This multi-functionality reduces the need for separate dedicated connection elements, simplifying the overall structure despite the complex vertical integration.
3Reliability
If the height of back-side bumps is increased to improve stacking efficiency, then the connection reliability between stacked chips is improved, but the passivation pattern stability becomes more challenging
Solution Approach 1:
The passivation pattern is designed with varying thicknesses at different locations: thicker regions provide enhanced stability and support where needed (particularly around through electrode openings and under bumps), while thinner regions reduce unnecessary material and allow for better bump protrusion. This localized variation in passivation thickness maintains structural stability while accommodating the increased bump height required for reliable stacking connections.
Data Source
AI summary
A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern.