Through-Electrode Chip Layout for Void-Free Package Stacking
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Solution Overview
Problem
Existing semiconductor chips and packages face challenges in reducing size while minimizing processing defects, particularly due to the difficulty in reducing the pitch of through electrodes without compromising the spacing between connection electrodes, leading to voids and bridging issues during stacking.
Innovation Solution
The semiconductor chip design includes through electrodes with a specific array arrangement, where the centers of front and rear surface connection electrodes are positioned farther from the central region than the corresponding through electrodes, increasing the pitch of these electrodes to prevent voids and defects during stacking, allowing for a smaller chip size and reduced defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the pitch of through electrodes is reduced to decrease chip size, then the chip area is reduced, but voids and bridging defects occur during stacking due to insufficient spacing between connection electrodes
Solution Approach 1:
The patent applies different pitch values to different regions of the electrode array. The first pitch value is used for through electrodes in the first array region, while a larger second pitch value is used for connection electrodes in the second array region. This local differentiation allows the chip area to be minimized while ensuring sufficient spacing for reliable stacking connections, preventing voids and bridging defects.
2Reliability
If the pitch of connection electrodes is increased to prevent voids and bridging, then the chip area increases, but the chip size cannot be reduced
Solution Approach 1:
The electrode array is segmented into at least two distinct array regions: a first array region for through electrodes with a first pitch value, and a second array region for connection electrodes with a second pitch value. This segmentation allows independent optimization of pitch values for different functional requirements, enabling small chip area while maintaining reliable stacking connections.
3Manufacturing precision
If the spacing between through electrodes and connection electrodes is increased to prevent defects, then the chip area increases, but chip miniaturization is compromised
Solution Approach 1:
The patent implements region-specific pitch values where the second array region (connection electrodes) has a larger pitch than the first array region (through electrodes). This local quality approach ensures that connection electrodes have sufficient spacing for precise manufacturing and reliable stacking, while through electrodes can be more densely packed, thereby minimizing overall chip area while maintaining manufacturing precision.
Data Source
AI summary
A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.