Through-Electrode Testing via Copper Post Bumps and Conductive Film
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Solution Overview
Problem
In the manufacturing of semiconductor devices with through-electrodes, it is challenging to effectively test all pins (through-electrodes) due to their miniaturization and close pitch, making it difficult to identify defective pins, especially when power source/GND pins are electrically coupled, leading to issues in open/short tests.
Innovation Solution
A method involving the formation of copper post bumps on a semiconductor chip and corresponding bumps on the back surface, with a conductive film connecting them, allowing for electrical short-circuiting to facilitate probing and testing of all through-electrodes, even those with narrow pitches, thereby enabling comprehensive testing of through-electrodes without damaging the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If probing is conducted directly to terminals on the surface and back surface of a thin logic chip, then testing of through-electrodes can be performed, but the chip may be damaged due to its thinness and the difficulty of handling
Solution Approach 1:
A carrier board is introduced as an intermediary component between the probing system and the logic chip. The carrier board provides a stable mounting platform with extended surfaces that allow probing to be performed on the carrier board rather than directly on the fragile chip terminals, thus preventing chip damage while enabling reliable testing of through-electrodes
2Reliability
If power source/GND pins are electrically coupled to perform testing, then comprehensive electrical testing can be conducted, but it becomes difficult to identify which specific pins are defective
Solution Approach 1:
The carrier board introduces separate test signal paths that segment the testing process. By providing dedicated test electrodes and signal routing on the carrier board, the system can selectively test individual pins or groups of pins independently, allowing defective pins to be identified even when power source/GND pins are electrically coupled for functional testing
Data Source
AI summary
Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.