Through Electrode Testing in Stacked Semiconductor Chips
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for testing three-dimensional semiconductor chips with through silicon vias (TSVs) are inefficient in detecting connection failures, leading to prolonged test times and reduced reliability.
Innovation Solution
A semiconductor chip design that includes a first and second semiconductor device stacked with through electrodes, where a test mode drives sequential patterns of logic levels through the electrodes to generate test data, compare logic levels, and selectively turn on inverters based on comparison signals to detect normal or abnormal operation of the through electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing methods are used for three-dimensional semiconductor chips with TSVs, then the testing process is simple, but the detection of connection failures is inefficient and test time is prolonged
Solution Approach 1:
The patent applies preliminary action by pre-configuring specific test circuits (including test voltage sources, current measurement circuits, and resistance measurement circuits) within the semiconductor chip before actual testing. These circuits are prepared in advance to enable rapid and accurate detection of TSV connection failures without requiring complex external testing equipment or prolonged test procedures, thus improving reliability while reducing test time.
2Productivity
If conventional testing methods are used for three-dimensional semiconductor chips with TSVs, then the testing procedure is straightforward, but test efficiency is reduced
Solution Approach 1:
The patent merges multiple testing functions into integrated test circuits that are built into the semiconductor chip structure. The test voltage source, current measurement circuit, and resistance measurement circuit are combined within the same chip, allowing simultaneous or sequential execution of multiple test operations. This integration significantly improves test efficiency by eliminating the need for separate external testing equipment while the modular design keeps the overall complexity manageable.
Data Source
AI summary
A semiconductor chip includes a first semiconductor device and a second semiconductor device stacked over the first semiconductor device. The second semiconductor device is electrically connected to the first semiconductor device via a plurality of through electrodes. In a test mode, the first semiconductor device is configured to drive a first pattern of logic levels and a second pattern of logic levels through the plurality of through electrodes, configured to compare logic levels of a plurality of test data generated by the first and second patterns from the first and second semiconductor devices to generate a detection signal indicating that the plurality of through electrodes operated normally or abnormally.