Through-Electrode Via Geometry for Reliable Semiconductor Interconnects
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving reliable electrical connections and efficient signal transfer due to the limitations of conventional solder balls and solder bumps, particularly in high-integration designs where smaller transistors lead to increased power consumption and reduced operating characteristics.
Innovation Solution
The semiconductor device incorporates a through electrode that penetrates the substrate and interlayer dielectric layer, with a unique arrangement of vias and conductive patterns in the intermetal dielectric layer, including a first via with a circular shape and a second via with a bar shape, optimizing the aspect ratio and contact area to enhance electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional solder balls or solder bumps are used for electrical connection, then the device structure is simple, but the signal transfer speed is slow and electrical reliability is insufficient
Solution Approach 1:
The electrical connection path is segmented into multiple components: through electrode penetrating the substrate, interlayer dielectric layer, and multiple wiring patterns with vias. This segmentation allows each component to be optimized independently for electrical performance while maintaining overall structural integrity.
Solution Approach 2:
The invention transitions from a two-dimensional surface mounting (solder balls/bumps) to a three-dimensional through-electrode structure that penetrates the substrate vertically. This dimensional change enables faster signal transfer and improved electrical reliability by creating direct through-substrate connections.
2Area of stationary object
If the transistor size is reduced to achieve higher integration, then the device size decreases, but power consumption increases and operating characteristics deteriorate
Solution Approach 1:
The invention changes the electrical connection parameters by implementing through electrodes with optimized dimensions (first width greater than second width), multiple vias with different aspect ratios, and controlled contact areas. These parameter changes improve electrical characteristics and reduce power consumption without requiring larger transistor sizes.
3Reliability
If via width is increased to reduce contact resistance, then electrical conductivity improves, but the aspect ratio decreases and manufacturing precision becomes more challenging
Solution Approach 1:
The invention applies different via width characteristics at different locations: the first via has a greater first width for reduced contact resistance at the through electrode interface, while the second via has a smaller second width for easier manufacturing. This local differentiation optimizes both electrical performance and manufacturability.
Data Source
AI summary
A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.