Through-Electrode Via Layout for Lower Contact Resistance
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving reliable electrical connections and reduced contact resistance due to the limitations of conventional solder balls and solder bumps, particularly in high-density integration and three-dimensional mounting configurations.
Innovation Solution
The semiconductor device incorporates a through electrode penetrating the substrate and interlayer dielectric layer, with a unique arrangement of vias and conductive patterns in the intermetal dielectric layer, featuring a bar-shaped second via with a greater width in the second direction to enhance electrical connectivity and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional solder balls or solder bumps are used for electrical connection, then the device structure is simple, but the contact resistance is high and electrical reliability is poor
Solution Approach 1:
The connection structure is divided into multiple segments: through electrode, intermetal dielectric layer, vias, and conductive patterns. This segmentation allows each component to be optimized independently, with the through electrode providing mechanical support and the vias/conductive patterns providing low-resistance electrical pathways, thereby improving overall electrical reliability while managing complexity through modular design
Solution Approach 2:
The invention transitions from conventional two-dimensional surface mounting to three-dimensional vertical integration. The through electrode penetrates the substrate vertically, and multiple wiring layers are stacked in the vertical dimension, enabling faster signal transfer and improved electrical characteristics by utilizing the third dimension for signal routing
2Reliability
If the width of the second via is increased to reduce contact resistance, then the electrical characteristics improve, but the area occupied in the intermetal dielectric layer increases
Solution Approach 1:
The via width is optimized locally based on functional requirements. The second via, which connects to the through electrode, has a greater width to reduce contact resistance at this critical interface. Other vias in the same intermetal dielectric layer may have different widths suited to their specific connection needs, allowing localized optimization without uniformly increasing the area occupied by all vias
Data Source
AI summary
A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.