Through-Electrode Chip Structure for Thin Stacked Package Reliability
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Solution Overview
Problem
Existing semiconductor chips face challenges in achieving thin thickness and small size while maintaining effective electrical connections, particularly in stacked configurations, due to issues with insulating layer thickness and void formation during manufacturing processes.
Innovation Solution
The semiconductor chip design includes through electrodes with specific spacing and connection electrodes that exceed twice the insulating layer thickness, along with a metal-containing thin film layer with an undercut, ensuring stable electrical connections and reduced resistance in power supply paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the insulating layer thickness is reduced to achieve thinner chip profiles, then chip thickness is improved, but void formation increases during manufacturing
Solution Approach 1:
The patent applies preliminary anti-action by designing the through electrode spacing to be greater than twice the insulating layer thickness before manufacturing occurs. This pre-designed spacing prevents void formation by ensuring adequate room for insulating material deposition and curing, addressing the void issue before it can occur during the manufacturing process.
Solution Approach 2:
The patent changes the critical parameter of through electrode spacing to be greater than twice the insulating layer thickness. This parameter modification allows the insulating layer to be made thinner while maintaining sufficient space to prevent void formation, thus resolving the contradiction between thin chip profiles and manufacturing reliability.
2Area of moving object
If through electrodes are placed closer together to reduce chip size, then chip area is improved, but electrical connection stability deteriorates
Solution Approach 1:
The patent establishes a specific parameter relationship where the distance between through electrodes exceeds twice the insulating layer thickness. This parameter setting optimizes the balance between minimizing chip area and maintaining electrical connection stability, allowing compact designs without compromising connection reliability.
Solution Approach 2:
The insulating layer serves as an intermediary element between closely spaced through electrodes. By ensuring the electrode spacing is greater than twice the insulating layer thickness, the patent allows the insulating material to effectively mediate between electrodes, providing both electrical isolation and mechanical support for stable connections.
3Manufacturing precision
If the insulating layer is made thinner to reduce chip thickness, then manufacturing precision is improved, but void formation increases
Solution Approach 1:
The patent applies preliminary anti-action by pre-determining the through electrode spacing to be greater than twice the insulating layer thickness. This pre-planned spacing configuration prevents void formation by ensuring adequate space for complete and uniform insulating material deposition, counteracting the tendency toward voids that arises when using thinner insulating layers.
Solution Approach 2:
The patent modifies the spacing parameter between through electrodes to be greater than twice the insulating layer thickness. This parameter change enables the use of thinner insulating layers with improved manufacturing precision while preventing void formation, as the increased spacing provides sufficient room for complete material coverage.
Data Source
AI summary
A semiconductor chip may include: a body portion with a front surface and a rear surface; a pair of through electrodes penetrating the body portion; an insulating layer disposed over the rear surface of the body portion and the pair of through electrodes; and a rear connection electrode disposed over the insulating layer and connected simultaneously with the pair of through electrodes, wherein a distance between the pair of through electrodes is greater than twice a thickness of the insulating layer.