Selective Through-Gate Ion Implantation for Transistor Threshold Voltage Control
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Solution Overview
Problem
Existing methods for creating integrated circuits with transistors of different threshold voltages require separate well masks and ion implanting operations for each region, which is inefficient and increases the complexity of the manufacturing process.
Innovation Solution
The use of selective through-gate ion implanting to selectively implant dopants into the channel regions of transistors, allowing for different threshold voltages in regions with a common well doping, thereby eliminating the need for separate well region implants and reducing the number of required mask steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate well masks and separate ion implanting operations are used for each region, then transistors with different threshold voltages can be achieved, but the manufacturing process complexity increases and efficiency decreases
Solution Approach 1:
The patent merges the well formation and threshold voltage adjustment into a single ion implantation operation. By using a gate mask instead of separate well masks, the process combines what were previously distinct steps (well implantation and threshold voltage implantation) into one unified process, thereby reducing manufacturing complexity while maintaining the ability to achieve different threshold voltages across regions
Solution Approach 2:
The gate structure serves multiple functions: it acts as both the transistor gate electrode and as a mask during the ion implantation process. This multi-functionality eliminates the need for separate well masks, simplifying the manufacturing process while still enabling precise control over threshold voltage differentiation in different regions
2Manufacturing precision
If separate well masks and ion implanting operations are used for each region, then different threshold voltages can be achieved, but the number of manufacturing steps increases
Solution Approach 1:
The patent combines multiple ion implantation operations into a single operation. By performing well formation and threshold voltage adjustment simultaneously through one ion implantation step using the gate as a mask, the process reduces the total number of manufacturing steps, thereby improving productivity and manufacturing efficiency without sacrificing threshold voltage control precision
3Manufacturing precision
If separate well masks are used for each region, then selective doping can be achieved, but the process time and manufacturing complexity increase
Solution Approach 1:
The gate structure is utilized as a dual-purpose component: it functions as both the operational gate electrode and as a masking layer during ion implantation. This eliminates the need for separate well masks, reducing the number of photolithography and etching steps required, thereby decreasing process time while maintaining selective doping precision through the gate's geometric definition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of transistors with distinct threshold voltages in integrated circuits without the need for separate well region implants, simplifying the manufacturing process and potentially improving operational efficiency by allowing transistors to operate at different voltage levels.
Implementation Method 1
implanting conductivity dopants through the second gate into the second channel region to adjust a threshold voltage of a second transistor
Data Source
AI summary
A first transistor and a second transistor are formed with different threshold voltages. A first gate is formed over the first region of a substrate for a first transistor and a second gate over the second region for a second transistor. The first region is masked. A threshold voltage of the second transistor is adjusted by implanting through the second gate while masking the first region. Current electrode regions are formed on opposing sides of the first gate and current electrode regions on opposing sides of the second gate.