Semiconductor Through-Hole Isolation Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The continuous shrinking of critical dimensions in semiconductor manufacturing leads to increased parasitic capacitance, which negatively impacts the performance and reliability of semiconductor structures by reducing operating speed and yield.
Innovation Solution
A manufacturing method for a semiconductor structure involves forming a first isolation layer that covers the sidewall layer, removing the sidewall layer to create a gap, and ensuring the gap is completely sealed by the first isolation layer, thereby eliminating the need for additional sealing steps and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the critical dimension is continuously shrunk to reduce interconnection line distance, then the integration density is improved, but the parasitic capacitance increases
Solution Approach 1:
The patent extracts and removes the sidewall layer material between adjacent interconnection lines to create gaps. This extraction eliminates the harmful parasitic capacitance forming medium while maintaining the shrunk critical dimension for high integration density.
Solution Approach 2:
The patent applies different treatments to different regions: the gap regions between interconnection lines are cleared of sidewall material to reduce capacitance, while the interconnection lines themselves maintain their shrunk dimensions for high density. This local differentiation resolves the contradiction between density and capacitance.
2Productivity
If a wet process is used to remove the sidewall layer, then the removal speed is improved, but residues are generated affecting manufacturing precision
Solution Approach 1:
The patent replaces the wet chemical process with a plasma-based process. The plasma process removes sidewall material through ion bombardment and chemical reactions, achieving both high removal efficiency and clean surfaces without residues that would compromise gap sealing precision.
Solution Approach 2:
The patent changes the removal process parameters from wet chemistry to plasma physics parameters (ion energy, plasma composition, power density). This parameter transformation enables residue-free removal while maintaining high productivity, resolving the precision-speed contradiction.
3Device complexity
If the first isolation layer does not completely cover the sidewall layer top, then the deposition process is simplified, but the gap sealing is improper increasing parasitic capacitance
Solution Approach 1:
The patent performs preliminary action by ensuring the first isolation layer completely covers the sidewall layer top surface before gap formation. This preliminary complete coverage prevents any potential capacitance pathways, eliminating the need for additional sealing steps and simplifying the overall process while ensuring reliability.
Solution Approach 2:
The first isolation layer serves multiple functions simultaneously: it acts as a barrier layer during deposition, provides complete gap sealing to prevent capacitance, and serves as an etch stop layer. This multi-functionality resolves the contradiction between process simplicity and sealing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces parasitic capacitance, improves the yield of semiconductor structures, and enhances the operating speed and reliability by ensuring thorough removal of the sidewall layer and stable sealing of the gap.
Implementation Method 1
providing a plasma source, causing an ion beam generated by the plasma source to react with the sidewall layer after passing through the first isolation layer and form reaction byproducts
Implementation Method 2
causing an ion beam generated by the plasma source to react with the sidewall layer after passing through the first isolation layer
Data Source
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AI summary
Provided are manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a base with an electrical contact layer therein; forming an insulating layer on the base, the insulating layer having a through hole penetrating the insulating layer, and the through hole exposing a surface of the electrical contact layer; forming a sidewall layer on a sidewall of the through hole; forming a first isolation layer, the first isolation layer covering a surface of the sidewall layer and an exposed surface of the insulating layer; removing the sidewall layer to form a gap between the first isolation layer and the insulating layer; and forming a conducting layer filling the through hole, the conducting layer being electrically connected to the electrical contact layer. Using the manufacturing method of a semiconductor structure according to an embodiment of the present disclosure, parasitic capacitance in a semiconductor structure can be effectively reduced.