Through-Hole Passivation for Reliable III-V Solar Cell Insulation

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Solution Overview

Problem

Existing methods for insulating through-contact holes in solar cells face challenges with defects and undercuts, leading to unreliable electrical insulation and potential shading issues, particularly in Metal Wrap Through (MWT) solar cells.

Innovation Solution

A passivation method involving chemical vapor deposition of a dielectric insulating layer on the top, bottom, and side walls of through-holes in semiconductor wafers, using a conformal layer deposition process to ensure complete coverage and application of multiple layers with different materials or stoichiometries to enhance adhesion and reduce pinhole density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If plasma-enhanced vapor deposition (PED) is used to apply insulating layers to through-hole sidewalls, then deposition can be achieved, but 40% of the insulating layers exhibit defects

Engineering Contradiction:
Improveinsulating layer qualityVSAvoidinsulating layer defect rate
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary actions by first smoothing the through-hole sidewalls using chemical-mechanical polishing (CMP) before depositing the insulating layer. This preliminary surface preparation removes undercuts and creates a uniform surface, preventing defects that would otherwise form during subsequent deposition processes.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the deposition parameters by using atmospheric pressure chemical vapor deposition (APCVD) instead of plasma-enhanced vapor deposition (PED). This parameter change in the deposition process eliminates the 40% defect rate associated with PED while maintaining effective insulating layer formation on the through-hole sidewalls.

Inventive Principle:
Principle #35Parameter changes

2Illumination intensity

If through-contact holes are created in solar cells, then front shading is reduced, but reliable insulation from sub-cells becomes difficult to achieve

Engineering Contradiction:
Improvefront shadingVSAvoidelectrical insulation
Core Design Contradiction:
Illumination intensityVSReliability

Solution Approach 1:

The patent applies preliminary surface smoothing using chemical-mechanical polishing (CMP) to create uniform sidewalls before insulating layer deposition. This preliminary action eliminates undercuts that would compromise insulation reliability, ensuring continuous insulating coverage while maintaining the through-contact hole's function of reducing front shading.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs a composite approach by combining mechanical polishing with chemical vapor deposition. The CMP process prepares the surface while the APCVD process forms the insulating layer, creating a composite process flow that achieves both low shading and reliable electrical insulation through the complementary actions of these two material processing techniques.

Inventive Principle:
Principle #40Composite materials

3Reliability

If smooth sidewalls free of undercuts are created in through-contact holes, then closed insulating layers can be formed, but additional process steps are required

Engineering Contradiction:
Improveinsulating layer continuityVSAvoidprocess steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the surface preparation and insulating layer formation into an integrated process sequence. By combining chemical-mechanical polishing with atmospheric pressure chemical vapor deposition in a unified process flow, the patent achieves continuous insulating coverage without requiring separate, complex steps for undercut removal and insulating layer application.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the deposition parameters from plasma-enhanced to atmospheric pressure chemical vapor deposition. This parameter change simplifies the overall process by eliminating the need for complex plasma generation equipment and additional process steps, while still achieving the required smooth sidewall coverage and continuous insulating layer formation.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method achieves reliable insulation within through-holes without additional effort, reducing pinhole density and improving the integrity of the insulating layer, thereby enhancing the electrical performance and reliability of solar cells.

Implementation Method 1

Application of a dielectric insulating layer by chemical vapor deposition to the top of the semiconductor disk, the bottom of the semiconductor disk and the side wall of the through-hole

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Implementation Method 2

By means of vapor deposition it is possible to achieve a conformal layer deposition, so that not only the top and bottom surfaces, but also the adjacent areas of the side surface of the through-hole are fully coated

Methodology Applied
Scientific EffectVapor deposition: Physical Vapour Deposition

Data Source

PatentEP3787043B1Passivation method for a through hole of a semiconductor wafer
Publication Date: 2026.03.04 AZUR SPACE SOLAR POWER
  • EP3787043B1 patent drawingFigure 1~3

AI summary

Passivation method for a through-hole of a semiconductor wafer comprising at least the steps of: providing a semiconductor wafer with a top, a bottom and comprising several solar cell stacks, each solar cell stack comprising a Ge substrate forming the bottom of the semiconductor wafer, a Ge subcell, at least two III-V subcells in the aforementioned order and at least one through-hole extending from the top to the bottom of the semiconductor wafer with a continuous side wall and an oval perimeter in cross-section, and applying a dielectric insulating layer by chemical vapor deposition to the top of the semiconductor wafer, the bottom of the semiconductor wafer and the side wall of the through-hole.