Through-Hole Seed Layer Roughness for High-Aspect-Ratio Interposers

Solution Overview

Problem

The challenge of forming conductor layers in through holes of interposers or substrates with increasing aspect ratios due to smaller line widths and pitches, which affects adhesion and electrical connectivity in 2.5D or 3D packaging of electronic devices.

Innovation Solution

A manufacturing method involving the formation of a substrate with through holes, followed by a first seed layer and an electrochemical reaction to create a second seed layer with a surface roughness of 1 nm to 1 μm, enhancing adhesion for a conductor layer formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If through holes with high aspect ratio are formed due to smaller line widths and pitches, then manufacturing precision of fine features is improved, but adhesion between conductor layer and substrate deteriorates

Engineering Contradiction:

Improveline width and pitchVSAvoidadhesion between conductor layer and substrate

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

A first seed layer is formed on the substrate before conductor layer deposition, and an electrochemical reaction is performed to create a second seed layer with controlled roughness (1 nm to 1 μm) on its surface. This preliminary surface modification enhances adhesion between the conductor layer and substrate, enabling reliable conductor layer formation in through holes with high aspect ratios resulting from finer line widths and pitches.

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If through holes with high aspect ratio are formed, then manufacturing precision of fine features is improved, but ease of manufacture of conductor layer deteriorates

Engineering Contradiction:

Improveline width and pitchVSAvoidconductor layer formation

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

A first seed layer is formed on the substrate before conductor layer deposition, and an electrochemical reaction is performed to create a second seed layer with controlled roughness (1 nm to 1 μm) on its surface. This preliminary surface modification enhances adhesion between the conductor layer and substrate, enabling reliable conductor layer formation in through holes with high aspect ratios resulting from finer line widths and pitches.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The surface roughness of the second seed layer is precisely controlled within the range of 1 nm to 1 μm through electrochemical reaction. This parameter optimization balances adhesion enhancement with manufacturability, allowing conductor layers to be reliably formed in high aspect ratio through holes while maintaining process feasibility.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improves adhesion between the conductor layer and the substrate, allowing reliable conductor layer formation in through holes with high aspect ratios, thereby enhancing electrical connectivity and reducing production time.

Implementation Method 1

an electrochemical reaction is performed to form a second seed layer on the first seed layer

Methodology Applied

Scientific EffectElectrochemical reaction: Electrolysis

Data Source

PatentUS20260005151A1Electronic device

Publication Date: 2026.01.01 INNOLUX CORP

AI summary

An electronic device and a manufacturing method thereof are provided. The electronic device includes a substrate, a seed layer, and a conductor layer. The substrate has a first surface and a second surface opposite to the first surface. The substrate includes a through hole, and the through hole has a sidewall connected to the first surface and the second surface. The seed layer is disposed on the first surface, the second surface, and the sidewall. The conductor layer is disposed on the seed layer, and a roughness of a surface of the seed layer is greater than or equal to 1 nm and less than or equal to 1 μm.