Through Hole Design for Semiconductor Package Alignment

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Solution Overview

Problem

Conventional three-dimensional integrated circuit package technologies using through silicon via (TSV) face challenges in reliability and electrical characteristics due to signal loss and design constraints, particularly in the etching process for forming through holes, which can result in undesired etching damage and misalignment issues.

Innovation Solution

A semiconductor package design that includes a through hole with a first hole and a second hole at its bottom end, where the second hole has a maximum diameter less than the minimum diameter of the first hole, and a mask layer on the upper lateral surface, allowing for precise alignment and minimizing etching damage through the use of a mask pattern to form the second hole, ensuring accurate connection to the landing pad.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional through hole etching process is used to form through holes in three-dimensional integrated circuit packages, then the through holes can be formed to connect stacked semiconductor chips, but etching damage and misalignment issues occur that reduce reliability and electrical characteristics

Engineering Contradiction:
Improvereliability of semiconductor packageVSAvoidalignment precision of through hole
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The through hole formation process is segmented into two distinct stages: first forming a larger first hole through the semiconductor substrate and dielectric layer, then forming a smaller second hole through the wiring layer that overlaps with the first hole. This segmentation allows each hole to be optimized for its specific function - the first hole provides structural penetration while the second hole ensures precise alignment with the landing pad, thereby resolving the contradiction between reliability and manufacturing precision

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first hole is formed in advance before the second hole. This preliminary action establishes a guide structure that facilitates subsequent precise alignment of the second hole with the landing pad. By preparing the first hole beforehand, the process ensures that the final through hole configuration achieves both structural integrity and precise electrical connection, addressing the alignment precision issue while maintaining reliability

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If the through hole diameter is reduced to improve alignment precision, then connection accuracy to landing pad improves, but etching damage increases and manufacturing difficulty rises

Engineering Contradiction:
Improvealignment precision of through holeVSAvoidetching damage
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The hole formation is divided into two segments with different diameter requirements: the first hole has a larger diameter that minimizes etching damage while providing structural penetration, and the second hole has a smaller diameter that ensures precise alignment. This segmentation allows each segment to be optimized independently - the first hole avoids excessive etching damage by being larger, while the second hole achieves precision without requiring the entire through hole to be small

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the through hole structure have different diameter qualities: the upper portion (first hole) has a larger diameter suitable for minimizing etching damage in the substrate and dielectric layer, while the lower portion (second hole) has a smaller diameter optimized for precise alignment with the landing pad. This local quality differentiation resolves the contradiction by allowing each region to have the diameter appropriate for its specific function

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11373932B2Semiconductor packages including through holes and methods of fabricating the same
Publication Date: 2022.06.28 SAMSUNG ELECTRONICS CO LTD
  • US11373932B2 patent drawing
  • US11373932B2 patent drawing
  • US11373932B2 patent drawing

AI summary

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first wiring layer, a first semiconductor substrate on the first wiring layer, a first dielectric layer on the first semiconductor substrate, a landing pad in the first wiring layer, a through hole that penetrates the first semiconductor substrate, the first dielectric layer, and the first wiring layer and exposes the landing pad, the through hole including a first hole and a second hole on a bottom end of the first hole, the second hole having a maximum diameter less than a minimum diameter of the first hole, and a mask layer on an upper lateral surface of the through hole.